Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2000-01-05
2004-02-24
Hjerpe, Richard (Department: 2774)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S098000
Reexamination Certificate
active
06697041
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a display drive device including a plurality of cascade connected drive circuits for driving a display element such as a liquid crystal display element according to an image data signal, and further relates to a liquid crystal module incorporating such a display drive device.
BACKGROUND OF THE INVENTION
A display drive device used in a conventional liquid crystal display device includes, as shown in
FIG. 14
, source driver LSI (Large Scale Integrated circuit) chips
51
and gate driver LSI chips
52
that are cascade connected and mounted on individual TCPs (Tape Carrier Packages)
53
to act as a plurality of drive circuits for driving a liquid crystal panel
54
. Further, the display drive device, together with the liquid crystal panel
54
, constitutes a liquid crystal module. Note that a TCP refers to a thin package including a tape film onto which an LSI chip is attached.
The source driver LSI chips
51
and the gate driver LSI chips
52
have output terminals electrically connected via TCP wiring on the TCPs
53
to output terminals of the TCPs
53
for output to the liquid crystal panel
54
. The output terminal of the TCPs
53
to the liquid crystal panel
54
is bonded by thermocompression via, for example, an ACF (Anisotropic Conductive Film) to a terminal (not shown) fabricated from ITO (Indium Tin Oxide) on the liquid crystal panel
54
to establish electrical connection therebetween. The liquid crystal panel
54
here is supposed to have 800×3 (RGB) [source side]×600 [gate side] pixels.
Each of the source driver LSI chips
51
drives 100×3 (RGB) pixels, and performs a 64 half-tone display. Therefore, here, eight source driver LSI chips
51
are cascade connected. Hereinafter, to distinguish each of the source driver LSI chips
51
from the others, those located in first to seventh stages will be referred to as first to seventh source drivers respectively, with the source driver LSI chip
51
located in the last stage referred to as an eighth source driver.
Meanwhile, two gate driver LSI chips
52
are cascade connected here. Hereinafter, to distinguish each of the gate driver LSI chips
52
from the other, those located in first and last stages will be referred to as first and second gate drivers respectively.
The display drive device includes a flexible substrate
55
on which a controller
56
is disposed; the TCPs
53
are electrically connected to the flexible substrate
55
. Specifically, the TCP wiring on the TCPs
53
that is electrically connected to the source driver LSI chips
51
and the gate driver LSI chips
52
is electrically connected via, for example, an ACF or soldering to the wiring on the flexible substrate
55
that is electrically connected to output terminals R, G, B, LS, Vcc, GND, Vref, VLS, SSPI, SCK, GCK, and GSPI (see
FIG. 15
) of the controller
56
.
This configuration allows various signals to travel to and from the source and gate driver LSI chips
51
and
52
through the wiring on the TCPs
53
and the flexible substrate
55
. The following description will explain various signal paths in the liquid crystal module.
First, the controller
56
provides, as outputs, image data signals R, G, and B at its output terminals R, G, and B, a clock signal CK at its output terminal SCK, and a latch signal LS at its output terminal LS; all these signals are then transmitted via the wiring on the flexible substrate
55
and the TCPs
53
, and supplied as common signals to each of the source driver LSI chips
51
.
Meanwhile, the controller
56
provides at its output terminal SSPI an output of a start pulse signal SPI which is transmitted via the wiring on the flexible substrate
55
and coupled to an input terminal SPin of the first source driver. After receiving the start pulse signal SPI, the first source driver transmits the start pulse signal SPI internally and provides an output of a start pulse signal SPO at its output terminal SPout. The output start pulse signal SPO is transmitted again via the wiring on the flexible substrate
55
and is coupled to input of a following stage, that is, an input terminal SPin of the second source driver. The start pulse signal SPI is similarly shifted and transmitted through further source drivers, until it reaches the last stage, that is, the eighth source driver.
Similarly, the controller
56
provides, as outputs, an LSI chip power supply voltage Vcc at its output terminal Vcc, 64 bit half-tone display reference voltages Vref
1
to Vref
6
at its output terminals Vref
1
to Vref
6
, and a brightness adjusting voltage (voltage for adjusting the voltage applied to the liquid crystal panel
54
) VLS at its output terminal VLS; all these signals, as well as a ground potential GND electrically connected to the output terminal GND of the controller
56
, are supplied commonly to each of the source driver LSI chips
51
. The wiring for transmitting the voltages Vcc, Vref
1
to Vref
6
, and VLS and the ground connection line (GND line) for transmitting the ground potential GND are disposed as power supply associated lines. Hereinafter, the voltages Vcc, Vref
1
to Vref
6
, and VLS, and the ground potential GND will be referred to as power supply associated voltages.
Meanwhile, the controller
56
provides, as outputs, a gate driver clock signal GCK at its output terminal GCK, an LSI chip power supply voltage Vcc at its output terminal Vcc, and reference voltages Vref
1
and
2
(Vref
1
and Vref
2
) at its output terminals Vref
1
and
2
for application to the liquid crystal panel
54
; all these signals, as well as a ground potential GND electrically connected to an output terminal GND of the controller
56
, are supplied commonly to each of the gate driver LSI chips
52
.
Further, the controller
56
provides at its output terminal GSPI an output of a gate driver start pulse signal GSPI which is coupled to an input terminal GSPin of the first gate driver. The first gate driver transmits the received start pulse signal GSPI internally in synchronization with the clock signal GCK and provides at its output terminal GSPout a start pulse signal GSPO which is coupled to an input terminal GSPin of a following stage, that is, of the second gate driver.
The following description will explain in detail a circuit arrangement of the source driver LSI chips
51
in accordance with the present invention in reference to the block diagram constituting FIG.
16
and also explain in detail operations of the source driver LSI chips
51
in reference to the signal timing charts constituting FIG.
17
. Note that although the following description will deal with only one of the eight source driver LSI chips
51
shown in
FIG. 14
, all the source driver LSI chips
51
function completely identically.
As shown in
FIG. 16
, the source driver LSI chip
51
is arranged to include a shift register
61
, a data latch circuit
62
, a sampling memory
63
, a hold memory
64
, a reference voltage generator circuit
65
, a D/A converter
66
, and an output circuit
67
.
The shift register
61
receives the start pulse signal SPI (see
FIG. 17
) provided as an output by the controller
56
at its output terminal SSPI and transmitted via the input terminal SPin of the source driver LSI chip
51
. The start pulse signal SPI is a synchronized signal having synchronization with horizontal synchronized signals of later-mentioned image data signals R, G, and B. The shift register
61
also receives the clock signal CK (see
FIG. 17
) provided as an output by the controller
56
at its output terminal SCK and transmitted via the input terminal CKin of the source driver LSI chip
51
.
The shift register
61
shifts the received start pulse signal SPI: more particularly, the shift register
61
starts shifting the start pulse signal SPI, with the start pulse signal SPI as a start pulse, when the clock signal CK received rises for the first time while the start pulse signal SPI is in high level.
The start pulse signal SPI shifted by the shift register
Sakaguchi Nobuhisa
Tamai Shigeki
Birch, Stewart, Kolash & Birch LLP
Hjerpe Richard
Nguyen Kevin
Sharp Kabushiki Kaisha
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