Computer graphics processing and selective visual display system – Display driving control circuitry – Physically integral with display elements
Reexamination Certificate
1999-08-26
2004-07-20
Liang, Regina (Department: 2674)
Computer graphics processing and selective visual display system
Display driving control circuitry
Physically integral with display elements
C345S060000
Reexamination Certificate
active
06765561
ABSTRACT:
BACKGROUND AND BRIEF DESCRIPTION OF THE INVENTION
The invention relates to cross-point matrix display devices and, more particularly, to flat cross-point matrix display devices having integrated circuit chips thereon, and, still more particularly, AC gas discharge display and memory panels having integrally associated driving circuits.
There are numerous types of flat panel cross-conductor matrix display devices using gaseous discharge mediums (AC and DC types), liquid crystal display mediums, and electroluminescent mediums. A typical example of a gas discharge display panel of the type with which the present invention is concerned is disclosed in Baker et al. U.S. Pat. No. 3,499,167 which is incorporated herein by reference. Integrating solid-state addressing circuits and chips with edge extensions on such panels is likewise well known in the art as disclosed in Schmersal U.S. Pat. No. 3,668,688. An example of a flat direct current (DC) dot matrix plasma display panel with integrated circuit (IC) chips on edge extensions is found in Person U.S. Pat. No. 4,613,855. An example of a liquid crystal display is given in Kubota U.S. Pat. No. 4,145,120 and, an example of thin-film electroluminescent display panel drive is shown in Fujioka et al. U.S. Pat. No. 4,983,885. A gas discharge display/memory panel with selection and addressing circuits incorporated on edge extensions of the panel wherein the dielectric coatings on the conductors in the active area of the panel are extended a distance beyond the spacer sealant and holes or vias are formed in the dielectric which contains circuit components is illustrated in Schmersal U.S. Pat. No. 3,684,918.
Thus, the present invention is directed to improvements in flat panel display systems and, more particularly, to improvements in the electromechanical-physical aspects of integrated circuit chips and their coupling to such display panels.
According to the invention, gold bump-type dies (integrated circuit chips) are inserted in self-aligning dielectric fixtures or micro-sockets integrally formed with the glass panel structure and directly in contact with a panel electrode and input circuit traces for the driver integrated circuit chips. Holes or vias are formed in edge extensions of a thin glass dielectric layer down to thin film electrodes and electrode patterns on a non-conductive substrate. The holes are filled to form a thick film pad by back-filling same with conductive gold frit to a predetermined distance from the top of the dielectric hole or via, then the die or flip chip with gold bumps thereon are inserted in the micro-sockets thus formed and clamped in place.
According to one aspect of the invention, the display panel has thin-film circuit traces and chip input/output pad patterns added around the panel periphery at the same time as the panel electrodes are added or formed with vacuum deposition and photolithography. Then a thin layer of dielectric glass is screen-printed onto the panel covering the thin film electrodes and circuit traces.
In a preferred embodiment, the dielectric glass is the same dielectric glass used in an AC plasma display panel but, it will be appreciated that other non-conductive glasses or insulators can be applied over the circuit tracers or patterns of liquid crystal and/or electroluminescent panels and processed as described earlier. In the case of the AC gas discharge display panel, the glass dielectric is then selectively etched using well known etching techniques which have been developed for etching barrier structures in AC plasma displays. The selectively etched cavities form vias (holes or feed-throughs) from the surface of the dielectric glass to the thin film pad patterns at the chip and at the edge connections for input signals and feed-throughs between chips where high voltage pulses and pulse current grounds can be routed.
Further, in a preferred embodiment, the glass dielectric covering extends to the edge of the glass panel and on top of the glass dielectric layers are screened-printed thick film conductive pads to accept external interconnect cable pads. The thick film pads extend over the vias and fill them up to create a connection from the external cable (flex circuit) over to the chip's pads. The thick film pads can be extended into the circuit traces which cross over other signal paths (under the dielectric glass) to feed-throughs which are filled up with the thick film conductors to complete a connection from the external cable to the chip's pads. The thick film gold referred to herein is applied as a paste although also containing a glass frit material. The paste is fired after application to the panel and the thick film conductor structure essentially becomes fused into and integral with the panel structure thus sealing the thin film conductors from contamination by ambient conditions.
The vias at the chip's pads are backfilled with thick film gold to a height which allows the chip bumps to settle into a detent when it is precisely in a correct mounting position. The detent holds the chip in the X, Y position, even in demanding shock and vibration environments. In the Z direction (e.g., perpendicular to the plane of the panel), an appropriate force will be asserted by wire spring clips which clamps around the edge of the panel. The flip chip on-glass devices which are mechanically clamped in place can be readily removed for service or when defective or to upgrade the drive chips.
REFERENCES:
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patent: 3684918 (1972-08-01), Schmersal
patent: 4145120 (1979-03-01), Kubota
patent: 4597617 (1986-07-01), Enochs
patent: 4613855 (1986-09-01), Person et al.
patent: 4677458 (1987-06-01), Morris
patent: 4887760 (1989-12-01), Yoshino et al.
patent: 4949147 (1990-08-01), Bertelink
patent: 4998665 (1991-03-01), Hayashi
patent: 5015191 (1991-05-01), Grabbe et al.
patent: 5754171 (1998-05-01), Stoller
patent: 5995088 (1999-11-01), Stoller
Circuits Assembly Magazine, pp. 25-33, May 1991.*
“Bumps”, ICP-TP-682. p23.*
“Active & Passive Base Device Interconnections”, Electron Packaging, 2-pgs, Dec. 1989.*
“Assembly Process Comparison”, 7-pgs, 1992.
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