Display device having a built-in memory

Computer graphics processing and selective visual display system – Display driving control circuitry – Controlling the condition of display elements

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345 28, 345190, 345200, 345203, 3642372, 3642454, 364DIG1, G06F 314

Patent

active

054127777

ABSTRACT:
A timing generator 12' applies a control signal SC1 consisting of a row address strobe signal RAS1, a column address strobe signal CAS1 and a writing control signal WE1 to a control input C of a DRAM 31 while it also applies a control signal SC2 consisting of a row address strobe signal RAS2, a column address strobe signal CAS2 and a writing control signal WE2 to a control input C of a DRAM 32. The control signals SC1and SC2 are produced in accordance with the least significant bit LSB of an inside address MA and independent of each other. The display data reading operation can be performed on each of memories (DRAMs) independent of each other, and therefore, the total period for the display data reading can be shortened, and accordingly, a saving of time allows an interruption of a longer period of the display data writing operation during the display period, and thus, a time for a display data renewal can be shortened.

REFERENCES:
patent: 4471461 (1984-09-01), Boone

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