Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2007-09-11
2007-09-11
Liang, Regina (Department: 2629)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S204000
Reexamination Certificate
active
10656333
ABSTRACT:
In a buffer that outputs an analog voltage Vout to be applied as a driving voltage to a pixel capacitance in a display region of an active-matrix liquid crystal display device, a CMOS circuit for generating this analog voltage includes four Pch transistors (QP0to QP3) connected in parallel and four Nch transistors (QN0to QN3) connected in parallel. When charging the pixel capacitance, a bias current is reduced and the driving capability is lowered by control with selector switches (SP1to SP3) at a time at which the large driving capability at the beginning of the charging is not necessary anymore. And when discharging the charge that has accumulated at the pixel capacitance, the bias current is reduced and the driving capability is lowered by control with selector switches (SN1to SN3) at a time at which the large driving capability at the beginning of the discharging is not necessary anymore. With this configuration, it is possible to reduce the power consumption of the output buffer applying the analog voltage for image display to the capacitive load in the display panel.
REFERENCES:
patent: 6653900 (2003-11-01), Bu
patent: 6677923 (2004-01-01), Kajihara et al.
patent: 6753880 (2004-06-01), Kudo et al.
patent: 2002-149125 (2002-05-01), None
Aoki Toshiya
Kitagawa Daiji
Harness & Dickey & Pierce P.L.C.
Liang Regina
Sharp Kabushiki Kaisha
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