Display device controller and method

Details Display device controller and method Display device controller and method

1991-09-05

1993-07-20

Oberley, Alvin E.

Communications: electrical

Land vehicle alarms or indicators

Internal alarm or indicator responsive to a condition of the...

340799, G09G 106

Patent

active

052297586

ABSTRACT:
A display device controller with improved read performance comprises video memory, a video display control unit, video processing logic, a write buffer and a read buffer. The write buffer and read buffer are coupled between a CPU and the video memory for transferring information between the CPU and video memory. In the preferred embodiment, the read buffer further comprises an address latch, a control circuit, a first buffer, a second buffer, a multiplexer and a counter. The control circuit stores addresses in the address latch, reads video memory, and stores the data in the first and second buffers. The control circuit determines the output to the CPU by controlling the multiplexer. The control circuit is also responsive to the counter and the read buffer is partially disabled if the miss rate is a high to reduce the negative consequences of the additional information read by the control circuit.

REFERENCES:
patent: 4546350 (1985-10-01), Tanaka
patent: 4737780 (1988-04-01), Ishii
patent: 4773026 (1988-09-01), Takahara et al.
patent: 4893114 (1990-01-01), Ishii
patent: 4983958 (1991-01-01), Carrick

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