Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
1999-09-01
2001-08-28
Wu, Xiao (Department: 2774)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S098000, C345S100000, C345S182000
Reexamination Certificate
active
06281869
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a display device, and particularly to an image display device having the function of being capable of enlarging and reducing a video signal when the number of vertical pixels of the video signal inputted to the image display device is different from the number of vertical pixels of a display unit of the image display device.
2. Description of the Related Art
In an image display unit or device for a personal computer or the like, for example, standards are defined in the number of pixels of a display panel. A VGA standard, an SVGA standard, an XGA standard, an SXGA standard, and a UXGA standard (however, any of VGA, SVGA, XGA, SXGA and UXGA corresponds to the trademark of IBM Corporation), etc. are widely known as typical ones. However, there may be a case in which as in the case in which an image comprised of a video signal for VGA is displayed on a display panel set to the XGA standard, the number of the pixels of the video signal inputted to the device and the number of the pixels of the display panel differ from each other. In that case, it is necessary to display the video signal on the display panel in enlarged or reduced form.
There has heretofore been adopted a system for storing data lying in an area that one desires to display in enlarged form and writing the same data into a plurality of lines of the display device when it is desired to implement the display of the data in enlarged form in the vertical direction. However, the present system needs peripheral devices such as a memory, an A/D converter, etc. and hence the display device increases in size and becomes complex. Therefore, the following has been proposed as an enlargement or scale-up display method.
In this type of image display device having the scale-up display function, a mode signal indicative of either the normal display or the enlargement display is set within a gate driver. The driving of one gate line or the driving of a plurality of gate lines is switched according to the type of the mode signal within one horizontal period in which image data corresponding to one line is outputted. Thus, if the number of the gate lines driven during one horizontal period is one, then the normal display is done. When the plurality of gate lines are simultaneously driven within one horizontal period, the same image data corresponding to one line is displayed on a plurality of lines on a display screen, whereby the scale-up display in the vertical direction is done.
FIG. 4
is a timing chart for describing the operation of the gate driver employed in the image display device, wherein
FIG. 4A
is a timing chart in a normal mode, and
FIG. 4B
is a timing chart at a display twice that in an enlargement mode, respectively. In
FIG. 4B
, gage output waveforms of adjacent two lines, which are represented as X
1
and X
2
, and X
3
and X
4
, are identical to each other.
On the other hand, the liquid crystal display device or the like generally makes use of a method for adding auxiliary capacitances (Cs) to respective pixels for holding electrical charges during one scanning period. Several types are considered as the structures of the auxiliary capacitances. However, as a method of avoiding a reduction in opening rate without using capacitive electrodes for constructing the auxiliary capacitances, the structure of auxiliary capacitance so-called Cs on-gate structure is provided wherein pixel electrodes and gate lines are laid out so as to overlap with each other and the auxiliary capacitances are made up of these pixel electrodes and gate lines.
It was however impossible to apply the above-described scale-up display technique to the liquid crystal display device having the auxiliary capacitances each having the Cs on-gate structure. This is because since the gate line adjacent to the gate line for driving one pixel serves as one electrode of the auxiliary capacitance for the pixel in the Cs on-gate structure, the auxiliary capacitance does not function if the gate output waveform at the adjacent gate line is not rendered low in level upon writing of data into the pixel connected to one gate line (when the gate output waveform is rendered high in level). Since, however, the above-described scale-up display method sets the gate output waveforms at the adjacent two gate lines so as to be identical to each other, each auxiliary capacitance does not function.
SUMMARY OF THE INVENTION
With the foregoing problems in view, it is therefore an object of the present invention to provide a display device having enlargement display and reduction display functions, which is capable of being applied to an image display unit such as a liquid crystal display device or the like provided with auxiliary capacitances each having a Cs on-gate structure without hindrance.
According to one aspect of the invention, for achieving the above object, there is provided a display device having an enlargement display function, comprising: a driving circuit including, pulse generating means for generating a copying second clock pulse signal within one horizontal period in addition to an original clock pulse signal generated upon provision of the number of vertical pixels identical to a predetermined number of vertical pixels of a display unit when a video signal having the number of vertical pixels smaller than the predetermined number of vertical pixels is displayed in enlarged form on the display unit to which the predetermined number of vertical pixels is set and repeating the generation of these clock pulse signals every one horizontal periods; gate clock generating means for receiving the clock pulse signal from the pulse generating means to thereby generate a gate clock signal obtained by superimposing the total original clock pulse signal and the second clock pulse signal corresponding to a number obtained by subtracting the number of the vertical pixels of the video signal from the number of the vertical pixels of the display unit; and gate driving means for receiving the gate clock signal from the gate clock generating means to thereby generate a plurality of gate driving signals which are respectively brought to high levels with different timings in association with respective pulses in the gate clock signal and have high level periods equal in length to one another.
In the driving circuit employed in the display device of the present invention, which has the scale-up display function, the pulse generating means first generates an original clock pulse signal and a copying second clock pulse signal within one horizontal period and repeats the generation of these clock pulse signals every one horizontal periods. Next, the gate clock generating means generates a gate clock signal obtained by superimposing the total original clock pulse signal and the second clock pulse signal corresponding to a number obtained by subtracting the number of vertical pixels of a video signal from the number of vertical pixels of a display unit in order to generate a gate clock signal having pulses corresponding to the number of the vertical pixels of the display unit. Then, the gate driving means is supplied with the gate clock signal generated from the gate clock generating means to thereby generate a plurality of gate driving signals respectively brought to high levels with different timings in association with the respective pulses in the gate clock signal and having high level periods equal in length to one another.
Owing to such action, a plurality of gate lines are driven within one horizontal period and the same video data corresponding to one line is displayed on a plurality of lines on the display unit. Therefore, a scale-up display corresponding to the number of the vertical pixels of the display unit is done.
Since, at this time, the plurality of gate driving signals for driving the plurality of gate lines are respectively rendered high in level with the different timings and the adjacent two gate lines are not brought to the high level perfectly simultaneously as in t
Alps Electric Co. ,Ltd.
Brinks Hofer Gilson & Lione
Wu Xiao
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