Display device and scanning circuit testing method

Details Display device and scanning circuit testing method Display device and scanning circuit testing method

2005-06-21

2005-06-21

Patel, Paresh (Department: 2829)

Electricity: measuring and testing

Impedance, admittance or other quantities representative of...

Lumped type parameters

C324S763010, C345S100000

Reexamination Certificate

active

06909304

ABSTRACT:
Each of a gate driver and a source driver periodically receives a clock signal and a start pulse, where the start pulse has a certain width and is shifted as shift data in the gate driver or source driver in synchronism with the clock signal. A logic circuit composed of an NAND gate and an inverter receives the start pulse and the shift data, the shift data being the output that is supplied after a predetermined delay from the last stage with respect to the shift direction. The output of the inverter is used to test scanning circuits. This provides a display device and a scanning circuit testing method, which enable the scanning circuits to be judged both surely and quickly, without increasing the area or complexity of the circuit.

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patent: 6703856 (2004-03-01), Fujita
patent: 06-194421 (1994-07-01), None

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