Display device and its driving method

Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix

Reexamination Certificate

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Details

C345S092000, C345S100000

Reexamination Certificate

active

06232945

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a display device and its driving method.
2. Description of the Prior Art
Recently, liquid crystal display devices have been noticed as flat panel devices of light weight and low power consumption. In particular, an active matrix liquid crystal display device provided with a thin film transistor (referred to as TFT, hereinafter) at each display pixel has been widely used as various displays such as TV and OA (office automation), because high definition display pictures can be obtained without any cross-talk. In addition, recently, there exists such a trial that the liquid crystal display device is used as a projector type display device according to a demand of still larger-sized display pictures.
When the active matrix display device as described above is used as a projector of smaller size, lower cost, and lower power consumption, it is essential to reduce the size of its optical system. Further, it is also necessary to reduce the size of the liquid crystal display device itself as small as about 3 inches, for instance.
Therefore, in the above-mentioned display device, there exists a trial of forming both a display pixel section and a driving circuit section for driving respective display pixels on the same substrate integral with each other.
On the other hand, it has become important to allow the display device to correspond to a plurality of image or video standards, for instance such that a picture having an aspect ratio of 4:3 based upon computer image signals is displayed on a display device composed of pixels having an aspect ratio of 16:9. In this case, it is considered that the number of the horizontal pixels including the horizontal blanking period of video signals is smaller than the number of the display pixels for constructing one horizontal pixel line on a display panel. In the case as described above, non-display data are displayed at the display pixels where corresponding video signals do not exist. In this case, as the method adopted on the driving circuit side, although it may be considered to bury the non-display data previously during the horizontal scanning period of the video signals, by changing the driving frequency of the video signals by use of a frame memory, the cost of this method is relatively high.
As another method, it may be considered to prepare both the display data and the non-display data and to select the display data or the non-display data for each pixel on the display device side in conformity with the video standard. The method of driving the display device as described above is disclosed SID 93 DIGEST p.383 to p.386 “A 1.9-in, 1.5-M pixel Driver Fully-Integrated Poly-Si TFT LCD for HDTV Projection”, for instance, in which a driving circuit mainly composed of shift registers for transferring video signals in sequence is used. In this method, however, it is difficult to switch the signal lines driven in the display panel in conformity with the video signal standard.
SUMMARY OF THE INVENTION
With these problems in mind, therefore, it is the object of the present invention to provide a display device and its driving method, which can display the non-display data in the non-display areas easily.
To achieve the above-mentioned object, the first aspect of the display device according to the present invention provides a display device, comprising: a display panel section including: a plurality of pixel electrodes arranged in a matrix pattern; a plurality of switching elements each arranged in correspondence to each pixel electrode; a plurality of scanning lines each connected in common to said switching elements corresponding to said pixel electrodes arranged in a same row direction, for transmitting a control signal for opening and closing said common-connected switching elements simultaneously; a plurality of video signal lines for transmitting video signals to said pixel electrodes arranged in a same column direction via said corresponding switching elements, respectively; and a plurality of opposing electrodes each arranged so as to be opposed to each of said pixel electrodes; and a video signal line driving circuit for generating a first timing signal according to a reset signal received before video data are received; for selecting non-display data transmitted in synchronism with the reset signal on the basis of the first timing signal; for transmitting the selected non-display data to said video signal line corresponding to the first timing signal; after that, for selecting the transmitted video data on the basis of a second timing signal; and for transmitting the selected video data to said video signal line corresponding to the second timing signal.
Here, it is preferable that said video signal line driving circuit comprises: a plurality of logic circuits, each for outputting the first or second timing signal on the basis of n-bit address signals and the reset signal; and a plurality of selecting circuits, each for selecting the video data or the non-display data on the basis of an output of said logic circuit.
Further, it is preferable that said video signal line driving circuit comprises: a plurality of logic circuits, each for outputting the first or second timing signal on the basis of n-bit address signals; a plurality of first selecting circuits, each for selecting the non-display data on the basis of the first timing signal; and a plurality of second selecting circuits, each for selecting the video data on the basis of the second timing signal.
Further, it is preferable that said video signal line driving circuit comprises: a logic circuit including: a shift register circuit composed of a plurality of cascade-connected flip-flops and responsive to a start pulse, for transferring the start pulse to the succeeding-stage flip-flop in sequence in synchronism with a clock signal; and a reset circuit for outputting the first timing signals and the second timing signals on the basis of an output of each-stage flip-flop of said shift register circuit and the reset signal; and a selecting circuit for selecting the video data or the non-display data on the basis of the first timing signals and the second timing signals.
Further, it is preferable that the display device further comprises switching means connected between a predetermined-stage flip-flop and the succeeding-stage flip-flop of said shift register circuit; for switching a first circuit connection for selecting an output of the predetermined-stage flip-flop to a second circuit connection for selecting a pulse signal obtained by bypassing the start pulse inputted to the first-stage flip-flop or vice versa, according to an aspect ratio of a display picture; and for transmitting the selected signal to the succeeding-stage flip-flop.
Further, it is preferable that said logic circuit further comprises means for, when said switching means switches the first circuit connection to the second connection for selecting the bypassed pulse signal, inhibiting the second timing signals from being outputted on the basis of the outputs of a plurality of said flip-flops including the first to predetermined stage flip-flops.
Further, it is preferable that said display panel section comprises: an array substrate formed with said pixel electrodes, said switching elements, said scanning lines, and said video signal lines; an opposing substrate formed with said opposing electrodes; and a liquid crystal layer sandwiched between said array substrate and said opposing substrate.
Further, it is preferable that said video signal line driving circuit is formed on said array substrate.
Further, the second aspect of the present invention provides a display device, comprising: a display panel section including: a plurality of pixel electrodes arranged in a matrix pattern; a plurality of switching elements each arranged in correspondence to each pixel electrode; a plurality of scanning lines each connected in common to said switching elements corresponding to said pixel electrodes arranged in a same row direction, for tran

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