Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2007-12-04
2007-12-04
Shankar, Vijay (Department: 2629)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S098000
Reexamination Certificate
active
10565251
ABSTRACT:
A display apparatus and a method for driving the display apparatus that are capable of suppressing image quality degradation resulting from delay in sampling pulses or from waveform rounding thereof and image quality degradation caused by coupling between the signal line and the common line and that between the signal line and the scan line even when the simultaneous sampling number is increased. The start pulse HST has a pulse width that includes a plurality of pulse widths of the clock pulses HCK and HCKX, for example, two pulse widths. The clock pulses DCK have four phases. Large margins α1and α2in the phase relationship between each of the clock pulses DCK1to DCK4and each of transfer pulses used for extracting the clock pulses DCK1to DCK4are assured. As a result, even if delay or waveform rounding occurs in the clock pulses DCK1to DCK4, sampling pulses SP1to SP6with a constant pulse width equal to that of each of the clock pulses DCK1to DCK4can be generated without being affected by the delay or waveform rounding.
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Harano Tamaki
Kobayashi Hiroshi
Shankar Vijay
Sonnenschein Nath & Rosenthal LLP
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