Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2000-08-16
2002-11-05
Chang, Kent (Department: 2673)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S098000, C345S092000
Reexamination Certificate
active
06476790
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a driver circuit, and more particularly, to a driver circuit of a display device.
2. Description of the Related Art
Techniques of manufacturing a semiconductor device, for example, a thin film transistor (TFT), which has a semiconductor thin film formed on an inexpensive glass substrate, have been making rapid progress in recent years. This is because there is an increasing demand for active matrix liquid crystal display devices (liquid crystal display devices).
In the active matrix liquid crystal display device, several hundred thousands to several millions of TFTs are arranged in matrix in a pixel portion, and electric charges going into and out of pixel electrodes that are connected to each TFT are controlled by the switching function of the TFTs.
Conventionally, thin film transistors employing an amorphous silicon film formed on a glass substrate are arranged in the pixel portion.
Further, in recent years, a structure is known in which quartz is utilized as a substrate and thin film transistors are manufactured from a polycrystalline silicon film. In this case, both a peripheral driver circuit and a pixel portion are constructed of the thin film transistors formed on the quartz substrate.
Still further, recently, also known is a technique in which thin film transistors using a crystalline silicon film are formed on a glass substrate by laser annealing or other techniques. Employment of this technique allows a pixel portion and a peripheral driver circuit to be integrated on the glass substrate.
Active matrix liquid crystal display devices are mainly used in notebook personal computers. Different from analog data used in the current television signals (NTSC or PAL) or the like, the personal computer outputs digital data to a display device. Conventionally, digital data from a personal computer are converted into analog data and then inputted into the active matrix liquid crystal display device, or to an active matrix liquid crystal display device that utilizes an externally attached digital driver.
Therefore, a liquid crystal display device having a digital interface capable of directly inputting digital data from outside is in the spotlight.
Here, a portion of a source driver of the liquid crystal display device having a digital interface that is recently in the spotlight is shown in FIG.
17
. In
FIG. 17
, reference numeral
8000
denotes a shift register circuit and reference numeral
8100
denotes a digital data latch circuit. The shift register
8000
generates a timing signal on the basis of a clock signal (CLK), a clock back signal (CLKB), and a start pulse (SP) which are supplied from outside, and then sends out the above timing signal to the digital data latch circuit
8100
. Based on the timing signal from the shift register circuit
8000
, the digital data latch circuit
8100
samples (takes in) and stores and holds digital data inputted from outside.
Note that a scanning direction switching circuit is included in the shift register circuit
8000
shown in FIG.
17
. The scanning direction switching circuit is a circuit for controlling the order of the output of the timing signal from the shift register circuit
8000
from left to right or from right to left in accordance with a scanning direction switching signal inputted from outside.
In a conventional shift register circuit such as the shift register circuit
8000
shown in
FIG. 17
, the shift register circuit
8000
is complicated and constructed by a large number of elements. In the present situation in which an active matrix liquid crystal display device with higher resolution is demanded, the surface area of the shift register circuit becomes larger as its resolution is improved. Thus, the number of elements constructing the shift register circuit is also increased.
Because of this increase in the number of elements, the production yield in the entire liquid crystal display devices becomes worse. Further, if the possessed surface area of the circuits becomes larger, it hinders the making of small scale liquid crystal display devices.
SUMMARY OF THE INVENTION
Accordingly, the present invention has been made in view of the above problems, and an object of the present invention is therefore to attain improvement in production yield and compactness of the active matrix liquid crystal display device by providing a driver circuit that is simple as well as possessing a small surface area.
FIG. 1
is referenced. A driver circuit of the present invention is shown in FIG.
1
. Reference numeral
100
denotes a shift register circuit and reference numeral
200
denotes a group of digital data latch circuits. Note that only 5 stages of the shift register circuit
100
and 1 bit of the group of digital data latch circuit
200
corresponding to the 5 stages of the shift register circuit
100
are shown in
FIG. 1
for explanation conveniences. However, the driver circuit of the present invention may have n stages of shift register circuits, and may also have m bits of the group of digital data latch circuits.
The shift register circuit
100
has a plurality of register circuits
110
,
120
,
130
,
140
, and
150
. An explanation is given here taking the register circuit
110
as an example. The register circuit
110
has a clocked inverter circuit
111
and an inverter circuit
112
. In addition thereto, the register circuit
110
has a signal line
113
and the parasitic capacitance of the signal line
113
may be considered as elements constructing the register circuit. Further, a clock signal (CLK), a clock back signal (CLKB), and a start pulse (SP) from outside are inputted to the shift register circuit
100
. These signals are fed to the register circuits
110
,
120
,
130
,
140
, and
150
.
The clocked inverter circuit
111
operates in the same period with the inputted clock signal (CLK) and the clock back signal (CLKB) to thereby output the inputted start pulse (SP) to the inverter circuit
112
. The inverter circuit
112
then outputs the inputted pulse signal to the signal line
113
and the register circuit
120
of the next stage. However, since a large number of elements are connected to the signal line
113
, its parasitic capacitance is large resulting in having a high load. The present invention actively utilizes this high load due to the large parasitic capacitance of the signal line
113
. Accordingly, timing signals are sequentially outputted at constant intervals from the register circuits
110
,
120
,
130
,
140
, and
150
.
The group of digital data latch circuits
200
has digital data latch circuits
210
,
220
,
230
,
240
, and
250
. An explanation is given taking the digital data latch circuit
210
as an example. The digital data latch circuit
210
has a first N-channel transistor
211
, a second N-channel transistor
212
, a P-channel transistor
213
, and inverter circuits
214
and
215
. Digital data and a reset signal (Res) are inputted to the digital data latch circuit
210
from outside. Further, a source or drain of the P-channel transistor
213
is connected to a first power source voltage (VDD_
1
). The first power source voltage (VDD_
1
) is set higher than the operation electric potential of the N-channel transistor.
Immediately before the start pulse (SP) is fed to the shift register circuit
100
, the reset signal (Res) is inputted to thereby feed the first power source voltage (VDD_
1
) to inverter circuits
214
,
224
,
234
,
244
, and
254
. In other words, a positive logic “1 (Hi)” signal is inputted.
The timing signal from the register circuit
110
outputted through the signal line
113
is inputted to the N-channel transistor
212
of the digital data latch circuit
210
, whereby the N-channel transistor
212
starts to operate. In addition, when a timing signal from the next stage register circuit
120
outputted through the signal line
123
is inputted to the N-channel transistor
211
of the digital data latch circuit
210
and the N-channel transistor
211
starts to
Chang Kent
Cook Alex McFarron Manzo Cummings & Mehler, Ltd.
Semiconductor Energy Laboratory Co,. Ltd.
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