Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2003-12-12
2008-08-19
Awad, Amr (Department: 2629)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
Reexamination Certificate
active
07414607
ABSTRACT:
In a structure in which a plurality of signals related to each other are supplied to a driving circuit in such a manner that at least one of the signals is supplied also to the other circuit, the present invention prevents change of phase relation between the plural signals due to difference in wiring load, without directly processing the signals with higher power consumption. The first and second clock signals SCK1and SCK2are supplied to the first data signal line driving circuit SD1, while the first clock signal SCK1is also supplied to the second data signal line driving circuit SD2in parallel. The wirings1and2for the respective signals are adjusted to have equal wiring load with a dummy wiring2provided in the wiring2, for solving uneven wiring load caused by difference of leading manner, the dummy wiring2constituting an additional capacitor section7, together with a liquid crystal layer and a counter electrode.
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Maeda Kazuhiro
Onda Mamoru
Washio Hajime
Awad Amr
Nixon & Vanderhye P.C.
Sharp Kabushiki Kaisha
Sherman Stephen G
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