Display device

Horology: time measuring systems or devices – Displays or display device details – Optical

Reexamination Certificate

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Details

C331S057000, C345S055000, C345S098000

Reexamination Certificate

active

11700876

ABSTRACT:
An oscillator circuit includes (2n+1) inverters connected in series when n is a natural number, an integrator circuit having an input terminal connected to an output terminal of a (2n+1)-th inverter and an output terminal connected to an input terminal of a first inverter, first and second p-type transistors connected in series between the input terminal of the first inverter and a first reference potential, and first and second n-type transistors connected in series between the input terminal of the first inverter and a second reference potential. An output voltage of a j-th inverter is applied to control electrodes of the first p-type transistor and the first n-type transistor. An output voltage of a k-th inverter is applied to control-electrodes of the second p-type transistor and the second n-type transistor. Symbol j is an odd number, k is an even number, and j<k=2n is satisfied.

REFERENCES:
patent: 3639790 (1972-02-01), Yatsushiro et al.
patent: 5180995 (1993-01-01), Hayashi et al.
patent: 5544120 (1996-08-01), Kuwagata et al.
patent: 5712652 (1998-01-01), Sato et al.
patent: 5898323 (1999-04-01), Suda
patent: 6373341 (2002-04-01), Morgan
patent: 2005/0110592 (2005-05-01), Lee
patent: 2005/0243246 (2005-11-01), Edwards et al.

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