Television – Synchronization – Automatic phase or frequency control
Reexamination Certificate
2000-08-25
2004-02-03
Luu, Matthew (Department: 2672)
Television
Synchronization
Automatic phase or frequency control
C348S571000
Reexamination Certificate
active
06686969
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to display devices which automatically adjust the phase of sampling of a video signal, and particularly to improvement for eliminating the effect of jitter appearing in the phase of sampling to realize sampling at a proper phase.
2. Description of the Background Art
FIG. 12
is a block diagram showing the structure of a conventional display device as a background of the invention. This device is disclosed in Japanese Patent Application Laid-Open No. 11-177847 (1999), which is constructed as a liquid crystal display device which automatically adjusts the phase of sampling of an input analog video signal.
The input video signal is converted into digital form in an A/D converter
71
. A video signal processing circuit
72
applies gamma correction etc. to the video signal in digital form and also converts the video signal into a proper form for an input signal to a liquid crystal panel
73
. A PLL circuit
76
includes a voltage-controlled oscillator (VCO)
77
and a frequency divider
78
, which multiplies the horizontal sync signal HD, one of the sync signals inputted with the video signal, to generate a clock having the same period as the video period. The divisional ratio of the frequency divider
78
determines the ratio of multiplication of the generated clock.
A phase correcting circuit
79
corrects the phase of the clock generated by the PLL circuit
76
and supplies a sampling clock VCLK to the A/D converter
71
. The A/D converter
71
samples the video signal for digitization in synchronization with the sampling clock VCLK. The video signal digitized by the A/D converter
71
in each period of the sampling clock VCLK (=video period) is alternately referred to as left data DL and right data DR.
An operating unit
80
calculates an absolute difference value &Dgr;D=abs (DL−DR) for every two periods of the sampling clock VCLK; the absolute difference value is the absolute value of a difference between the left data DL and the right data DR. It also calculates a maximum absolute difference value Dmax=Max(&Dgr;D) which is a maximum value of the absolute difference values &Dgr;D in one frame. The sign “abs ( )” represents the absolute value.
A CPU
81
has a comparator
82
for comparing the maximum absolute difference values Dmax and a control circuit
83
for controlling the phase correcting circuit
79
on the basis of the result of the comparison to maximize the maximum absolute difference value Dmax. The control circuit
83
also serves to set the ratio of multiplication of the PLL circuit
76
in accordance with the format of the input video signal (e.g. VGA format etc.)
A timing generating circuit
74
generates a horizontal reference signal and a vertical reference signal indicating the starting points of horizontal and vertical scans on the basis of the sampling clock VCLK, horizontal sync signal HD and vertical sync signal VD. A liquid crystal driving circuit
75
generates a driving signal for driving the liquid crystal panel
73
. The liquid crystal panel
73
receives the driving signal from the liquid crystal driving circuit
75
and the video signal from the video signal processing circuit
72
and displays the picture represented by the video signal.
FIGS. 13A
to
13
D,
14
A to
14
D and
15
A to
15
D are explanation diagrams illustrating the operation of adjusting the phase of the sampling clock VCLK. In these explanation diagrams, it is assumed for the sake of simplicity that the video signal represents an image pattern which alternately varies for each pixel as white, black, white, black . . . It is also assumed that the phase correcting circuit
79
can vary the phase of the clock within a variable-phase range of 0 to 360° corresponding to the video period and in
32
steps from setting
0
to setting
31
. In these diagrams, “ADC sampling” shows the timing of sampling by the A/D converter
71
.
FIGS. 13A
to
13
D show the characteristic of the maximum absolute difference value Dmax exhibited when the input video signal has a waveform close to a sine wave,
FIGS. 14A
to
14
D show that exhibited when the input video signal has a waveform intermediate between a sine wave and a rectangular wave, and
FIGS. 15A
to
15
D show that exhibited when the input video signal has a waveform close to a rectangular wave. It is assumed that the sampling clock VCLK and the video signal are in the phase relation shown in the diagrams when the phase value or the phase correction value set in the phase correcting circuit
79
is zero (that is, when the amount of delay by correction is 0°). The general principle of the description below is applicable whatever the phase relation is.
When the input video signal is close to a sine wave (
FIGS. 13A
to
13
D), the maximum absolute difference value Dmax varies in upwardly convex curves as the phase value varies, where the phase value at the maximum corresponds to the optimum value and the phase value at the minimum corresponds to the worst value. As the video signal approaches a rectangular wave (
FIGS. 14A
to
14
D and
15
A to
15
D), the maximum absolute difference value Dmax holds a maximum or nearby value in a wider range of the phase value. Accordingly, the optimum phase value is preferably obtained by detecting the worst value, i.e. a phase value at which the maximum absolute difference value Dmax becomes minimum, and setting the opposite phase shifted by 180° from the worst value as the optimum phase value.
The conventional display device shown in
FIG. 12
operates as explained above to automatically optimize the phase of sampling of the input analog video signal.
However, due to the effect of general frequency characteristic of the circuit, the input video signal approaches a sine wave as the video frequency (the reciprocal of the video period) becomes higher and approaches a rectangular wave as it becomes lower. Further, clock jitter usually appears in the clock outputted from the PLL circuit
76
, which becomes larger as the video frequency becomes lower. Accordingly, when the video frequency is low, it is difficult to find the optimum phase value in the conventional display device of FIG.
12
.
FIGS. 16A
to
16
D are explanation diagrams showing this problem, which shows an example of the characteristic of the maximum absolute difference value Dmax with a clock including jitter of 10%. As shown in
FIGS. 16A
to
16
D, due to the effect of the jitter, the valleys of the maximum absolute difference value Dmax disappear and the maximum absolute difference value Dmax maintains a constant value almost in the whole range of the phase value. Then the optimum phase value cannot be found. Such effect of jitter becomes more serious as the video frequency becomes lower.
SUMMARY OF THE INVENTION
The present invention has been made to solve the aforementioned problem of conventional devices, and an object of the invention is to obtain a display device which can eliminate the effect of jitter appearing in the phase of sampling of the video signal so as to realize sampling at a proper phase regardless of the video frequency.
According to a first aspect of the present invention, a display device comprises: a sampling portion for sampling a video signal at a rate of a half period which is ½ times a video period of the video signal; a selecting portion for outputting as a display signal every other sampled signal which is the video signal sampled at the rate of the half period; a phase adjusting portion for adjusting the phase of the sampling performed by the sampling portion within a given variable-phase range; an absolute difference value calculating portion for calculating an absolute difference value which is, when the sampled signals are numbered with respect to one of the sampled signals in order of sampling time, the absolute value of a difference between an odd-numbered sampled signal and the next even-numbered sampled signal; a maximum absolute difference value calculating portion for calculating a m
Hara Kouichirou
Murakami Yasuo
Birch & Stewart Kolasch & Birch, LLP
Luu Matthew
NEC-Mitsubishi Electric Visual Systems Corporation
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