Display controller provided with dynamic output clock

Details Display controller provided with dynamic output clock Display controller provided with dynamic output clock

2007-04-10

2007-04-10

Zimmerman, Mark (Department: 2628)

Computer graphics processing and selective visual display system

Computer graphic processing system

C345S100000, C348S511000

Reexamination Certificate

active

10291833

ABSTRACT:
The present invention provides a display controller for scaling an input source image. The display controller dynamically adjusts the output clock so line buffer requirement is reduced to a minimum to balance input and output image timing for image scaling or non-scaling to destination devices. The present invention supports up-scaling and down-scaling or bypass. The blocks of the line buffer operates in a continuous and cyclical manner according to the status signal generated by the line buffer status detector and the output clock. As a result, any buffer overrun or underrun condition will be immediately corrected by the timing and therefore the number of blocks of line buffer are greatly reduced.

REFERENCES:
patent: 5739867 (1998-04-01), Eglit
patent: 5977805 (1999-11-01), Vergnes et al.

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