Computer graphics processing and selective visual display system – Computer graphics processing – Attributes
Reexamination Certificate
2000-06-16
2003-11-11
Saras, Steven (Department: 2775)
Computer graphics processing and selective visual display system
Computer graphics processing
Attributes
C345S634000
Reexamination Certificate
active
06646651
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to an LSI for controlling the display of picture data such as letters or drawings and, more particularly, to a display system controller which is suitable for superposed display of a plurality of frames.
DESCRIPTION OF THE PRIOR ART
In accordance with a highly integrated memory LSI, the cost of a graphic display equipped with a high-capacity memory is dropped so that letter displays are processed by a full bit map. In accordance with the high detail of a display device, there is an increase in the quantity of information to be handled. In these displays, the display control of letters and drawings is handled by a special purpose LSI (or a CRT controller).
Specifically, the CRT controller functions to sequentially output memory addresses from the display starting address which is preset in conformity with the raster scan. The CRT controller has another function to output a synchronizing signal for driving the display system. A CRT controller of the prior art type for displaying data from a plurality of independent frames, is shown in
FIGS. 1 and 2
.
Prior Art Example 1
FIG. 1
shows the method for controlling refresh memories having a plurality of divided banks by means of a single CRT controller
13
. This CRT controller
13
is connected via an address bus
11
and a data bus
12
with a central processing unit (i.e., CPU) for generating refresh addresses for the display and a synchronizing signal for the CRT. A clock generator
14
feeds an operation clock to the CRT controller
13
and parallel-series converters
171
and
172
. An address selector
15
selects the display memory address, which is fed from the CRT controller
13
, during the display and the address bus
11
of the CPU during the non-display interval thereby to access the two refresh memory banks
161
and
162
. The data read out from the memories are converted independently of each other by the parallel-series converters
171
and
172
into series signals, which are superposed in a synthesizing circuit
18
.
Since the two memory banks are fed with the identical display address, according to the prior art system having the construction thus far described, the two frames to be superposed have to be of the same frame construction. Even in the case when the superposition is conducted only in one portion of the display frame, a memory capacity for two display frames is required which causes a problem that the memory efficiency is lessened. In the case when the frame is shifted by rewriting the display starting address, on the other hand, the two frames cannot be shifted independently of each other. Since, the contents of the refresh memories cannot be rewritten during the display, there is a defect that the drawing speed is slowed down.
Prior Art Example 2
FIG. 2
shows a method in which a plurality of CRT controllers shown in
FIG. 1
are used to individually control a plurality of memory banks. Two CRT controllers
131
and
132
conduct their synchronizing operations in response to an identical clock from the clock generator
14
and individually generate display memory addresses to access the refresh memories
161
and
162
. The data thus read out are converted by the parallel-series converters
171
and
172
into series signals so that a superposed image signal is generated in the synchronizing circuit
18
.
Since the addresses of the two display frames are controlled independently of each other, the frames can be shifted independently of each other, but there arises a problem that the numbers of parts and wirings required are so large that the scale of the system is accordingly enlarged. In case the superposition is conducted only in a portion of the display frame, on the other hand, the capacities of the refresh memories can be reduced. Because of the construction in which the memories for the individual frames are physically separated, however, the design has to be made in conformity with the maximum size of the superposed frame. Moreover, the drawing speed is slow because the contents of the refresh memories cannot be rewritten during the display as in the case of FIG.
1
. The prior art method belonging to that of
FIG. 2
, is disclosed in the specification of Japanese Patent Laid-Open No. 52-95926.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a display controller which can conduct the superposed display of a plurality of display frames with a simple construction.
According to a feature of the present invention, display addresses of n (i.e., an integer equal to or larger than 2) independent systems are generated during one display period so that data stored in the corresponding addresses are sequentially read out from a refresh memory in accordance with those display addresses and used for the superposed display.
In order to ensure the above feature, the display controller of the present invention is constructed to include:
(1) a timing processor receptive of a clock to generate a display address generating a timing signal having a timing prepared by dividing one display period by n; and
(2) a display processor stored with
n
groups of display starting addresses for sequentially generating display addresses corresponding to the respective groups, each time it receives the timing, with reference to the display starting addresses to output the display addresses to a refresh memory.
Table 1 tabulates the representative specifications of the display controller of the present invention. The present controller has a graphics drawing function to make a variety of drawings on a frame memory. More specifically, thirty eight kinds of drawing commands such as commands for drawing a straight line, circle and ellipse, painting out or copying.
An X-Y coordinate system is used for addressing a drawing point so that the load upon the development of an application software can be remarkably lightened. The frame memory has a high capacity of 2 megabytes at the maximum and can support a frame size of 2,048×2,048 dots for a 16-color display. The display controller has various display control functions such as frame dividing, smooth scrolling, magnifying or superposing functions.
TABLE 1
Specification of Display Controller
Items
Specifications
Operating Frequencies
1 MHz-8 MHz
1 MHz-6 MHz
1 MHz-4 MHz
Display Memory
For graphic: 2 Mbytes
Capacities
For characters: 128 Kbytes
Drawing Commands
38 kinds
Straight lines, squares,
polygons, circles, ellipses,
painting-out and copying
Drawing Functions
Address administration on X-Y
coordinates
Drawing function by patterns
Masking function by color
conditions
Drawing region administering
function
DMA transferring function
Drawing Speed
Common for monochromatic and
color
Linear drawing speed: 500
ns/dot (for 8 MHz)
Displaying Functions
Frame division: 3 horizontal +
1 window
Hor. and Vert. Smooth
scrolling
Magnified display (1 to 16
times in Hor. and Vert.
directions)
Superposition of frames
External Synchronism
Graphic cursor function
REFERENCES:
patent: 4104624 (1978-08-01), Hamada
patent: 4200869 (1980-04-01), Murayama et al.
patent: 4412294 (1983-10-01), Watts et al.
patent: 4467322 (1984-08-01), Bell et al.
patent: 4485378 (1984-11-01), Matsui et al.
patent: 4533910 (1985-08-01), Sukonick et al.
patent: 4574364 (1986-03-01), Tabata et al.
patent: 4692757 (1987-09-01), Tsuhara et al.
patent: 4710762 (1987-12-01), Yamada
patent: 4757310 (1988-07-01), Katsura et al.
patent: 4785296 (1988-11-01), Tabata et al.
patent: 0059349 (1982-09-01), None
patent: 3201614 (1990-05-01), None
Katsura Koyo
Maejima Hideo
Takeda Hiroshi
Antonelli Terry Stout & Kraus LLP
Bell Paul A.
Hitachi , Ltd.
Saras Steven
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