Computer graphics processing and selective visual display system – Display driving control circuitry – Adjusting display pixel size or pixels per given area
Reexamination Certificate
1998-06-04
2002-02-19
Saras, Steven (Department: 2775)
Computer graphics processing and selective visual display system
Display driving control circuitry
Adjusting display pixel size or pixels per given area
C345S003400, C345S698000, C345S003300
Reexamination Certificate
active
06348931
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a display control device and, more particularly, to switching of display modes.
2. Related Background Art
Conventionally, as display devices for host computer apparatuses such as personal computers (to be referred to as PCs hereinafter), workstations, and the like, raster-scan type so-called CRTs (Cathode-Ray Tubes) display devices are popularly used.
In recent years, flat-panel display devices such as liquid crystal panels, plasma displays, and the like are receiving a lot of attention in terms of space savings, energy savings, ergonomics, and the like.
The signal exchanged between the above-mentioned display device and host computer apparatus is a so-called video signal, i.e., a combined signal of an analog image signal and horizontal and vertical sync signals, or a composite signal thereof.
The video signal sent to the display device has a very large number of specifications (standards) depending on host computer apparatuses.
Especially, when a PC is used as the host computer apparatus, there are a plurality of different resolutions as those for the image to be displayed. For example, the following horizontal resolutions× vertical resolutions are available: 320×200 pixels, 640×400 pixels, 720×400 pixels, 640×350 pixels, 640×480 pixels, 800×600 pixels, 832×642 pixels 1,024×768 pixels, 1,152×870 pixels, 1,280×1,024 pixels, and the like.
Furthermore, even at identical resolution, there are a plurality of modes (display modes) using different horizontal and vertical sync signal frequencies. This is because the video signal sent to the display device has different standards depending on PCs, and has various resolutions, as described above. In this fashion, since the scan speed (scan frequency) per second varies depending on the resolutions and standards, the display mode must be selected to display images corresponding to various types of video signals mentioned above using an identical display device.
For this purpose, a display device having a function of automatically selecting the display mode (multiscan function) has been proposed.
This display device is a so-called multiscan display device. In such display device, a plurality of display modes corresponding to a plurality of different combinations of the sync signal frequencies and their polarity signals of the input video signals (input signals) are prepared, and the display parameters of these display modes are pre-stored in a ROM (Read Only Memory) or the like. The display device measures the sync signal frequency and its polarity signals of an actually input video signal, and acquires the display parameters of the display mode corresponding to the detected combination of the signals. Using these parameters, the display device measures the display resolution, horizontal and vertical blanking periods, and the like of the input signals, and makes predetermined setups.
However, when the above-mentioned multiscan display device does not store any display parameters of a display mode corresponding to the actually measured sync signal frequency and its polarity signal of the input signal, an image cannot be displayed satisfactorily. For example, no image can be displayed on the screen.
On the other hand, recently, PCs are popularly used in applications such as CAD (Computer Aided Design) and the like that require graphics display. Accordingly, the graphics display of computer displays is required to have high image quality. In order to satisfy such requirement, the following methods are available:
1. increase the display resolution
2. raise the frame (field) frequency
The former method can obtain a finer image, and the latter method allows a flicker-free display. For this reason, it is becoming a common practice for PCs to use displays which have SVGA display modes with resolutions as high as 800×600, 1,024×768, and 1,280×1024, in addition to the conventionally popular VGA mode with a resolution of 640×480. Furthermore, the vertical sync frequency tends to rise from 60 Hz to more than 70 Hz.
The video signal output from a workstation or PC is displayed on a high-resolution FLCD (Ferroelectric Liquid Crystal Display) as the above-mentioned flat-panel display as follows. That is, as described above, the display mode is identified from the sync signal sent from the computer, and the sync signal is separated into horizontal and vertical sync signals. Based on the identified display mode, FLCD dot clocks synchronous with the pixel clocks of the computer are reproduced using the separated horizontal sync signal, and an image signal is A/D-converted using the FLCD dot clocks. The obtained digital data is subjected to &ggr; characteristic adjustment and halftone processing, and that digital image data is transferred to an FLCD output controller, thus attaining a display.
In the display modes such as VGA, SVGA, XGA, and the like with lower resolutions, an enlarged interpolation display is made based on the identified display mode to display an image on the entire screen, by “oversampling” the horizontal effective display region of the video signal to 1,280 pixels that match the number of display line pixels of the FLCD as for expansion in the line direction, and performing a digital interpolation that maintains the aspect ratio as for expansion in the vertical direction.
However, when the video signal sent from the computer is displayed on the FLCD in an enlarged scale by interpolation on the basis of the above-mentioned oversampling, the following problem is posed. That is, since the analog video signal is sampled asynchronously to the pixel clocks of the host computer, a transient, sharply changing point is sampled between neighboring pixels. In this case, the dot clocks as the sampling clocks for A/D conversion are generated based on the horizontal sync signal, which normally includes jitter. Under the influences of such jitter, the dot clocks also unwontedly jitter. For this reason, mainly in case of a still image, the sampling points vary between neighboring pixels in units of frames, resulting in image quality deterioration such as flickering.
SUMMARY OF THE INVENTION
It is an object of the present invention to solve the above-mentioned problems.
It is another object of the present invention to satisfactorily display an image independently of the state of the input signal.
In order to solve the above problems and to achieve the above objects, according to one aspect of the present invention, there is provided a display control device for controlling a display device which displays an image corresponding to an input video signal, comprising detection means for detecting a state of the input video signal, mode setting means for setting a display mode of the display device among n different display modes corresponding to different states of the input video signal on the basis of an output from the detection means, and control means for controlling display operation of the display device in accordance with the display mode set by the mode setting means, wherein the mode setting means setting the display mode of the display device to be one of the n different display modes when the state of the input video signal detected by the detection means does not match any of the n different display modes.
It is still another object of the present invention to obtain a high-quality, interpolated image free from flickering.
Other objects and features of the present invention will become apparent from the following detailed description of the embodiments of the present invention taken in conjunction with the accompanying drawings.
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patent: 5031118 (1991-07-01), Morizot
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patent: 5592194 (1997-01-01), Nishikawa
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Sawada Masayuki
Suga Kazumi
Anyaso Uchendu O.
Canon Kabushiki Kaisha
Fitzpatrick ,Cella, Harper & Scinto
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