Computer graphics processing and selective visual display system – Plural display systems – Diverse systems
Reexamination Certificate
1998-11-19
2002-01-22
Wu, Xiao (Department: 2674)
Computer graphics processing and selective visual display system
Plural display systems
Diverse systems
C345S003200, C348S793000
Reexamination Certificate
active
06340959
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a display control circuit which is preferably applied to a portable information terminal that is an electronic appliance and an information-processing apparatus such as a personal computer, and which realizes the same display simultaneously both on a matrix display device installed in the portable information terminal or the information-processing apparatus and on a television receiver with a large screen size.
BACKGROUND OF THE INVENTION
For example, Japanese Laid-Open Patent Publication No. 282886/1986 (Tokukaishou 61-282886) discloses a typical prior-art technique in which, as described above, a portable information terminal or an image-processing apparatus is allowed to display images on an external television receiver with a larger screen size, in addition to its image on the matrix display device such as a liquid crystal display installed therein.
FIG. 17
shows the construction of an image display in accordance with the above-mentioned prior art.
In the prior-art technique, image data formed by a processing unit, image data picked up by a camera, or image data received by a television receiver is stored in a display memory
1
as RGB data. An address signal, released from a reading circuit
2
used for liquid crystal display or a reading circuit
3
used for monitoring display, and a control signal, such as a chip select signal CS and an output enable signal OE, are selectively switched by a switching circuit
4
, and inputted to the display memory
1
. The switching circuit
4
, which has received a selection signal between the liquid crystal display and the monitor from a register in response to a user's operation, carries out the corresponding switching between the address signal and the control signal released from the reading circuit
2
used for liquid crystal display and the reading circuit
3
used for monitoring display. RGB data, read from the display memory
1
in response to the address signal and the control signal from the switching circuit
4
, are commonly supplied to a television-signal encoder
6
and a liquid crystal display
7
through a data bus
5
.
A horizontal synchronous signal HSYNC, a vertical synchronous signal VSYNC, a data clock DCLK and an enable signal ENAB are inputted to the liquid crystal display
7
from the reading circuit
2
used for liquid crystal display. The liquid crystal display
7
, when “liquid crystal” is selected by the switching circuit
4
as its display output, receives the RGB data from the display memory
1
based on the control signal from the reading circuit
2
used for liquid crystal display, thereby carrying out an image display.
Control signals, such as a horizontal synchronous signal HSYNC, a vertical synchronous signal VSYNC and a pixel clock PXCLK, are supplied from the reading circuit
3
used for monitoring display to the television signal encoder
6
. The television signal encoder
6
, when “monitor” is selected as its display output, acquires the RGB data from the display memory
1
in accordance with the control signal, forms an analog video signal, and releases it to the television receiver
8
.
In this manner, image displaying on the liquid crystal display
7
that is integrally installed on the portable information terminal or the information processing apparatus and image displaying by means of the external television receiver
8
are selectively carried out. The display memory
1
, the reading circuit
2
used for liquid crystal display, the reading circuit
3
used for monitoring display, the switching circuit
4
and the television signal encoder
6
are integrally formed in a display control circuit
10
.
However, the problem with the above-mentioned prior-art technique is that simultaneous image displays are not available between the liquid crystal display
7
and the television receiver
8
. In this regard, so-called desktop-type and laptop-type information processing apparatuses, which allow various input operations by using the cursor, make it possible to carry out an input operation if image displaying is carried out either on the liquid crystal display
7
or the television receiver
8
. However, portable information terminals, which carry out input operations by touching the liquid crystal screen with a pen, hand or finger, have a problem in which when image displaying is being carried out on the television receiver
8
, no input operations are available. In particular, in the case when an explanation is given while updating display screens in an occasion such as a presentation, switching to “liquid crystal display” has to be made each time the screen is updated, so as to carry out input operations.
For example, Japanese Laid-Open Patent Publication No. 83798/1988 (Tokukaishou 63-83798) discloses another prior-art technique that can solve such a problem.
FIG. 18
shows this prior art. Here, in the construction of
FIG. 18
, those portions similar to and corresponding to the aforementioned construction of
FIG. 17
are indicated by the same reference numerals, and the description thereof is omitted.
In the prior-art technique, RGB data, which is sent from the display memory
1
through the data bus
5
, is commonly supplied to a liquid crystal data latch circuit
11
and a monitor data latch circuit
12
, and these data latch circuits
11
and
12
respectively carry out latch processes on the RGB data in response to latch timing from the aforementioned reading circuits
2
and
3
. Here, the “liquid crystal/monitor” selection signal, which is supplied from the register to the switching circuit
4
, serves as a signal for giving the address signal and the control signal from the reading circuits
2
and
3
to the display memory
1
in a time-division manner.
This arrangement allows the liquid crystal data latch circuit
11
and the monitor data latch circuit
12
to respectively read the RGB data from the common display memory
1
. The display memory
1
, the reading circuits
2
and
3
, the switching circuit
4
and the data latch circuits
11
and
12
are integrally formed in a display control circuit
20
, and the television signal encoder
6
is installed as a separated device from the display control circuit
20
. The RGB data, which has been latched by the liquid crystal data latch circuit
11
, is read in optimal reading timing for the liquid crystal display
7
, and supplied to the liquid crystal display
7
through a data bus
13
. Moreover, the RGB data, which has been latched by the monitor data latch circuit
12
, is read in optimal reading timing for the television receiver
8
, and supplied to the television signal encoder
6
through a data bus
14
.
As illustrated in
FIG. 18
, when the television signal encoder
6
is provided as the separated device, the number of terminals of the display control circuit
20
needs to be increased so as to correspond to the two systems of the data buses
13
and
14
for RGB data. Therefore, for example, in the case of six signal lines required for each color of R, G and B, the number of terminals required for the integrated circuits of the display control circuit
20
amounts to
36
, resulting in an increase in the number of terminals.
In this regard, as illustrated in
FIG. 17
, the solution to the above-mentioned problem is to integrally install the television signal encoder
6
in the integrated circuits of the display control circuit
20
; however, there are some cases in which the television signal encoder
6
can not be integrally installed in the display control circuit
20
and other cases in which it is considered to be more beneficial not to provide the built-in construction. One of the reasons is that it is difficult to create an ASIC which is mixedly provided with the television signal encoder
6
that is a digital encoder with an analog-circuit portion and the rest of the circuits, such as the display memory
1
and the reading circuits
2
and
3
, that are digital circuits, Moreover, the separated reading circuits
2
and
3
have to be provided, making the
Sharp Kabushiki Kaisha
Wu Xiao
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