Computer graphics processing and selective visual display system – Plural display systems
Reexamination Certificate
2005-04-05
2008-11-25
Shalwala, Bipin (Department: 2629)
Computer graphics processing and selective visual display system
Plural display systems
C345S002300, C345S004000, C345S531000, C345S536000, C345S537000
Reexamination Certificate
active
07456804
ABSTRACT:
A display control apparatus has a synchronizing signal generating section which generates a display synchronizing signal, a bus access control section which reads out video data for a plurality of system, one system at a time, from a local memory, a screen combining section which processes to combine video data which was readout, and video data for use in combining, sequentially, a buffer section which stores video data which was processed to be combined, and the video data for use in combining, a buffer control section which controls an access to the buffer section, a display IF section which reads out video data that the buffer section stores, and outputs the video data to each of display monitors in accordance with a display synchronizing signal, and display output selecting means which selects an output destination of video data for plural systems, which the display IF section outputs.
REFERENCES:
patent: 5710570 (1998-01-01), Wada et al.
patent: 6020863 (2000-02-01), Taylor
patent: 6184905 (2001-02-01), Hartog
patent: 6522309 (2003-02-01), Weber
patent: 2002/0149541 (2002-10-01), Shin
LCD/CRT 2D Graphic Subsystem Data Book, Version 0.08, May 26, 2000 (nVIDIA Corporation).
Kovalick Vince E
McDermott Will & Emery LLP
Panasonic Corporation
Shalwala Bipin
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