Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2000-01-25
2002-09-10
Shalwala, Bipin (Department: 2673)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S075200
Reexamination Certificate
active
06448948
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of flat panel display screens. More specifically, the present invention relates to the field of flat panel field emission displays (FEDs).
BACKGROUND OF THE INVENTION
Flat panel field emission displays (FEDs), like standard cathode ray tube (CRT) television sets, generate light by impinging high energy electrons on a picture element of a phosphor screen. The excited phosphor then converts the electron energy into visible light. However, unlike conventional television CRTs which use a single electron beam to scan across the phosphor screen in a raster pattern, FEDs use individual stationary electron sources for each pixel of the phosphor screen. Thus, a screen with a million color pixels has at least a million individual electron sources. There are three electron sources, each source consisting of many emitters, for each pixel in RGB color screen; one for red, one for green and one for blue. By using stationary electron sources instead of a scanning beam, the distance between the electron source and the phosphor screen can be made to be extremely small. Consequently, FED displays can be made to be very thin.
As mentioned, conventional CRT displays use electron beams to scan across the phosphor screen in a raster pattern. Specifically, the electron beams scan along a row in a horizontal direction and adjust the intensity according to the desired brightness of each picture element of that row. The electron beams then step in a column (vertical) direction and scan the next row until all the rows of the display screen are scanned. In marked contrast, in FEDs, a group of stationary electron sources are formed for each picture element (pixel) of the display screen. More specifically, the pixels of an FED flat panel screen are arranged in an array of horizontally aligned rows and vertically aligned columns. A portion
100
of this array is shown in FIG.
1
A. The boundaries of a respective pixel
125
are indicated by dashed lines and in this configuration include a red point, a green point, and a blue point. Three separate row lines
130
a
-
130
c
are shown. Each of the row lines
130
a
,
130
b
, and
130
c
is a row electrode for one of the rows of pixels in the array. A pixel row is comprised of all the pixels along one row line
130
. Each column of pixels may include three columns lines
150
: one for red, a second for green, and a third for blue. The column lines
150
control gate electrodes of the FED screen. When electron-emitting elements contained within the row electrode are suitably excited by adjusting the voltage of the corresponding row lines
130
(row electrodes) and column lines
150
(gate electrodes), electrons are emitted and are accelerated toward a phosphor anode
120
. The excited phosphors at the anode
120
then emit light.
In order to realize different gray scale levels, different voltages are applied to the column lines
150
. Brightness of the pixels depends on the voltage potential applied across the row electrode and the gate electrode. The larger the voltage potential, the brighter the pixel. In addition, brightness of the pixel depends on the amount of time the voltage potential is applied. The larger the amount of time a potential difference is applied, the brighter the pixel. In operation, all column lines
150
are driven with gray-scale data and simultaneously one row is activated. The gray-scale information causes the column drivers to assert different voltage amplitudes (amplitude modulation) to realize the different gray-scale contents of the pixel. This causes a row of pixels to illuminate with the proper gray scale data. This is then repeated for another row, etc., until the frame is filled.
During a screen frame refresh cycle (performed at a rate of approximately 60 Hz), one row is energized to illuminate one row of pixels for an “on-time” period. This is typically performed sequentially in time, row by row, until all pixel rows have been illuminated to display the frame. For each new row, the column data changes. Therefore, the column voltage must settle to a new voltage as each new row is asserted. For instance, if frames are presented at 60 Hz and the FED display has 480 rows in the display array, each row is energized every 34.8 &mgr;s. Consequently, an appropriate column voltage settling time is 10 &mgr;s. Since the columns are energized at a high rate, it is critical to ascertain that each column is energized at a near identical rate. Otherwise, if some columns have a slightly longer settling time than the others, the brightness across the screen will not be uniform which can cause unwanted screen artifacts such as vertical segments of different brightness.
Unfortunately, in prior art FED systems, it is difficult to eliminate such screen artifacts. The principal reason is attributed to manufacturing complications which cause column drivers to have different settling times.
FIG. 1B
illustrates this problem. As shown, the column driver
2
settles at a faster rate than column driver
3
, but slower than column driver
1
, causing the group of column lines driven by different column drivers to have disparate “on-time” windows. As a result, vertical segments of uneven brightness appear on the display. A means to cause the column drivers to settle to the same voltage at the same time eliminates this brightness variation problem. One prior art method of matching the settling times of the column drivers fabricates the column drivers from adjacent dies on the same wafer. This solution, however, is not practical because there is no guarantee that column drivers made from the same wafer have the same settling time. Further, if one column driver in a display malfunctions, the whole set of column drivers have to be replaced with others from the same wafer.
Accordingly, the present invention provides a mechanism and device for eliminating objectionable vertical segments of different brightness on an FED display. The present invention also provides a mechanism and device for normalizing the settling times of all the column drivers in a FED display. These and other advantages of the present invention not specifically mentioned above will become clear within discussions of the present invention presented herein.
SUMMARY OF THE INVENTION
A circuit and method are described herein for providing uniform display brightness by eliminating segments of uneven brightness in flat panel field emission display (FED) screen. Within the flat panel FED screen, a matrix of rows and columns is provided and electron emitters are situated within each row-column intersection. In one embodiment, rows are activated sequentially from the top most row down to the bottom row with only one row asserted at a time; and columns are driven to a new voltage level simultaneously as each row is asserted. When a proper voltage is applied across the row electrode and column electrodes, emitters release electrons toward a respective phosphor spot, causing an illumination point on the display.
According to one embodiment of the present invention, column lines of the FED screen are driven by column drivers. By measuring an output voltage of each column driver, the settling time of each column driver is then determined, and a signal representative of each settling time is generated. The signal is then used to deviate the settling time of the respective column driver towards a target settling time. As a result, the settling times of all the column drivers in the FED screen are normalized. Consequently, the brightness variation problem is eliminated.
In one embodiment of the present invention, the column drivers each comprises output amplifiers for forming output voltages for each column, and a dummy output amplifier for forming a dummy output voltage. Each column driver also comprises a phase-detector for comparing the dummy output voltage and a target reference signal, and for generating phase difference signal. The phase difference signal is then used to adjust bias current or bias voltage of output amplifiers within t
Candescent Intellectual Property Services Inc.
Patel Nitin
Shalwala Bipin
Wagner , Murabito & Hao LLP
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