Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
1997-03-13
2003-09-23
Hjerpe, Richard (Department: 2674)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S055000, C345S087000
Reexamination Certificate
active
06624798
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a display apparatus having a flat display panel, and more particularly to an improvement in a driver circuit which requires reduced electric power consumption for energizing address lines or data bus lines in such a display apparatus.
2. Description of the Prior Art
Flat display panels include an AC-type plasma display panel (hereinafter referred to as a PDP), a DC-type PDP, a liquid crystal display panel (LCD), and an electroluminescent (EL) panel. A feature common to these display panels is that data signals representing display data are supplied from a driver circuit to a plurality of vertical address lines (or data bus lines) and a plurality of horizontal scanning lines are successively energized to display the display data at pixels positioned at the points of intersection between the address lines and the scanning lines.
When the scanning lines are successively energized downwardly and the data signals representing display data on the respective scanning lines are applied to the address lines, the address lines are charged from an L level to an H level and discharged from an H level to an L level. When an image which comprises a zigzag grid pattern of energized pixels (white pixels) and de-energized pixels (black pixels) is displayed, the address lines are charged and discharged between H and L levels each time a shift is made from one scanning line to another scanning line. With respect to any adjacent two of the address lines, one of the address line is charged and the other discharged.
The conventional driver circuit for energizing the address lines energizes the address lines to an H level or an L level during a period in which a scanning pulse is applied to a scanning line. In a next scanning period in which a scanning pulse is applied to a next scanning line, the driver circuit energizes the address lines simultaneously to an H level or an L level.
When the address lines are energized, a predetermined amount of electric power is consumed. The amount of electric power which is consumed needs to be as small as possible for PDPs that effect a plasma discharge for image display. LCDs for use in portable computers are desired to consume a reduced amount of electric power.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a display apparatus having a flat display panel which consumes a reduced amount of electric power.
Another object of the present invention is to provide a display apparatus having a flat display panel which requires reduced electric power consumption for energizing address electrodes.
Still another object of the present invention is to provide a PDP display apparatus having a PDP which requires reduced electric power consumption for energizing address electrodes.
The inventor has noticed that when address lines are energized, capacitances between address electrodes and scanning electrodes confronting the address electrodes are charged and discharged, and also capacitances between adjacent address electrodes are charged and discharged, and has found a process of reducing the amount of electric power required to charge and discharge the capacitances between the adjacent address electrodes by improving the waveforms of drive pulses for the address electrodes.
For displaying a zigzag grid display pattern, described above, a capacitance between adjacent address lines is charged from one of the address lines and simultaneously discharged to the other address line, and hence the capacitance consumes a twofold amount of electric power. The consumed amount of electric power can be reduced to one half at most by forming a closed loop between the adjacent address lines through a power supply line (connected to a power supply or a ground). The principles of the process found by the inventor will be described later on.
The above objects of the present invention can be achieved by a display apparatus comprising a flat display panel having a plurality of address electrodes and a plurality of scanning electrodes extending transversely to the address electrodes and disposed in confronting relation to the address electrodes, a scanning electrode driver for successively supplying scanning pulses to the scanning electrodes with scanning timing, and an address driver for supplying address pulses according to display data to the address electrodes in synchronism with the scanning timing, wherein the address electrodes include first and second address electrodes disposed adjacent to each other, and the address pulse applied to the first address electrode rises and the address pulse applied to the second address electrode falls with a predetermined time difference therebetween.
The address driver may energize the address electrodes such that the address pulse applied to the second address electrode starts falling a predetermined time after the address pulse applied to the first address electrode starts rising.
Alternatively, the address driver may energize the address electrodes such that the address pulse applied to the first address electrode starts rising a predetermined time after the address pulse applied to the second address electrode starts falling.
The address driver may also energize the address electrodes such that the address pulse applied to the second address electrode starts falling after the address pulse applied to the first address electrode finishes rising.
Alternatively, the address driver may also energize the address electrodes such that the address pulse applied to the first address electrode starts rising after the address pulse applied to the second address electrode finishes falling.
The address driver may generate the predetermined time difference by energizing the address electrodes such that the address pulses applied to the first and second address electrodes rise at a gradient smaller than a gradient at which the address pulses applied to the first and second address electrodes fall.
Alternatively, the address driver may generate the predetermined time difference by energizing the address electrodes such that the address pulses applied to the first and second address electrodes rise at a gradient larger than a gradient at which the address pulses applied to the first and second address electrodes fall.
According to the present invention, the above objects can also be achieved by a PDP display apparatus comprising a flat display panel having a plurality of address electrodes and a plurality of scanning electrodes extending transversely to the address electrodes and disposed in confronting relation to the address electrodes with a discharge space defined therebetween, a scanning electrode driver for successively supplying scanning pulses to the scanning electrodes with scanning timing, and an address driver for supplying address pulses according to display data to the address electrodes in synchronism with the scanning timing, wherein the address electrodes include first and second address electrodes disposed adjacent to each other, and the address pulse applied to the first address electrode rises and the address pulse applied to the second address electrode falls with a predetermined time difference therebetween.
The address driver may be designed such that the predetermined time difference is effective to substantially reduce an amount of electric power consumed by the address driver to charge a capacitance between the first and second address electrodes.
The above and other objects, features, and advantages of the present invention will become apparent from the following description when taken in conjunction with the accompanying drawings which illustrate a preferred embodiment of the present invention by way of example.
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patent: 5483252 (1996-01-01), Shigeta
patent: 5541618 (1996-07-01), Shinoda
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patent: 5670974 (1997-09-01), Ohba et al.
patent: 5790092 (1998-08-01), Moriyama
Aoki Masami
Kawada Toyoshi
Koizumi Haruo
Fujitsu Limited
Hjerpe Richard
Nguyen Francis
Staas & Halsey , LLP
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