Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2000-04-17
2002-10-29
Mengistu, Amare (Department: 2673)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S214000
Reexamination Certificate
active
06473066
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an active matrix type liquid crystal display apparatus. More particularly, the present invention relates to a liquid crystal display apparatus in which a noise is not displayed as a regular pattern, if an interlaced scanning is performed for jumping over a horizontal display line every other line to write an image data, when an enlarged display is performed on an image display unit, and a display method.
2. Description of the Related Art
In an active matrix type liquid crystal display apparatus, characteristic errors of signal processors are averaged to improve the quality of display.
FIG. 1
is a configuration diagram showing an example of a liquid crystal display apparatus using this averaging operation.
An input image signal Sin is provided with analog R, G and B signals, and is inputted to a time base converter
101
. The input image signal Sin may be any of an interlace signal and a progressive signal. The time base converter
101
samples the successively supplied input image signal Sin through a sampling and holding circuit, and then divides the data into n sections in parallel to drop the frequency.
As the input image signal Sin becomes high accurate, an operation frequency of a sampling and holding circuit in an image display driver
104
becomes higher associated with the higher accuracy. Thus, it is difficult to attain a function of the image display driver
104
. As shown in
FIG. 1
, inner operations of the image display driver
104
can be performed in parallel by providing n input terminals for the image display driver
104
, in order to drop the operation frequency. The time base converter
101
performs a 2n-paralleling process on the input image signal Sin. So, the signals obtained by the 2n-paralleling process are processed in parallel to each other by 2n signal processors
1
to 2n to drop the operational frequency.
Here, a position at which the time base converter
101
starts sampling the input image signal Sin can be arbitrarily determined in accordance with an SP control signal Ssp
2
inputted to the time base converter
101
from a switching controller
106
. In short, a data processed by the sampling and holding circuit different for each frame is supplied to a particular pixel. This is an averaging principle.
In the switching controller
106
, its averaging period is set at a 2n vertical period and a 2n horizontal period. The vertical period corresponds to the 2n of the number of signal processors
1
to 2n. The horizontal period corresponds to the 2n of the number of signal processors
1
to 2n. The 2n vertical period and the 2n horizontal period will be described later.
The time base converter
101
performs a parallel time base conversion on the input image signal Sin to generate conversion image signals SC
1
to SC2n. The number of conversion image signals SC
1
to SC2n is equal to two times the division ratio n. The time base converter
101
is connected to 2n signal processors
1
to 2n which are connected parallel to each other. The time base converter
101
outputs the conversion image signals SC
1
to SC2n to the signal processors
1
to 2n, respectively.
The signal processors
1
to 2n perform a signal process, such as a &ggr; conversion, a data inversion and the like, on the conversion image signals SC
1
to SC2n, respectively, to thereby generate processed image signals SP
1
to SP2n.
The signal processors
1
to 2n are connected to a switching selector
103
. The switching selector
103
, in response to a selector signal Ssel
2
outputted from the switching controller
106
, selects half n signals from the image signals (the processed image signals SP
1
to SP2n) corresponding to 2n dots stored in the signal processors
1
to 2n. This is because the switching selector
103
samples the processed image signals corresponding to the latter n dots while the switching selector
103
outputs the processed image signals corresponding to the former n dots as image signals S
1
to Sn.
The switching selector
103
outputs the image signals S
1
to Sn divided into the n sections, from n output sections SO
1
to SOn. The image signal S
1
is outputted from the first output section SO
1
of the switching selector
103
, the image signal S
2
is outputted from the second output section SO
2
, and the image signal Sn is outputted from the n-th output section SOn.
The processed image signal processed by which number of signal processor among the signal processors
1
to 2n to be outputted as the image signal S
1
from the first output section SO
1
can be selected as desired. At this time, the processed image signals outputted as the image signals S
2
, S
3
to Sn from the second, third to n-th output sections SO
2
, SO
3
to SOn following the first output section SO
1
are selected such that they are arranged in order with respect to the processed image signal outputted as the image signal S
1
from the first output section SO
1
.
For example, the number of signal processors
1
to 2n is defined as 8 (n=4). Here, it is assumed that the processed image signal SP
3
outputted from the third signal processor
3
is outputted as the image signal S
1
from the first output section SO
1
of the switching selector
103
. In this case, the processed image signals SP
3
, SP
4
, SP
5
and SP
6
outputted from the signal processors
3
,
4
,
5
and
6
in the former period are outputted as the image signals S
1
to S
4
, from the first to fourth output sections SO
1
to SO
4
. Also in the latter period, the processed image signals SP
7
, SP
8
, SP
1
and SP
2
outputted from the signal processors
7
,
8
,
1
and
2
are outputted as the image signals S
1
to S
4
, from the first to fourth output sections SO
1
to SO
4
.
The image signals S
1
to Sn outputted from the output sections SO
1
to SOn of the switching selector
103
are supplied to the image display driver
104
. The image display driver
104
is provided with a plurality of blocks arrayed along an image display unit
105
composed of a liquid crystal panel and the like. The image display driver
104
outputs the image signals to the image display unit
105
, each time it samples the image signals S
1
to Sn divided into the n sections by the switching selector
103
by using an n-division clock signal, or after it completes sampling the image signals in one horizontal period.
The image signals S
1
to Sn outputted from the switching selector
103
are inputted to one terminal of the plurality of blocks of the image display driver
104
, and sequentially shifted to another block. Then, the image display driver
104
samples a pixel data of each block at a predetermined frequency.
The operation of the liquid crystal display apparatus shown in
FIG. 1
will be described below with reference to
FIGS. 2A
to
6
.
FIGS. 2A
to
2
H show averaging patterns generated by the switching controller
106
if the number of signal processors
1
to 2n is 8 (n=4), namely, formats
1
to
8
. One table described in each of
FIGS. 2A
to
2
H shows an averaging pattern in one frame. A horizontal axis indicates an order in a horizontal direction, and a vertical axis indicates an order in a vertical direction.
Numerals in the respective tables denote the numbers corresponding to the processed image signals SP
1
to SP
8
outputted from the selected signal processors
1
to
8
. A slant line portion indicates that the processed image signal SP
1
outputted from the first signal processor
1
is selected.
FIGS. 3A
to
3
H show display images when the averaging patterns of
FIGS. 2A
to
2
H are used, respectively. Numerals in respective tables indicate that the image data (processed image signals) SP
1
to SP
8
processed by the signal processors
1
to
8
corresponding to its number are displayed. A slant line portion indicates a position on the display screen of the image display unit
105
of the processed image signal SP
1
processed by the first signal processor
1
. A horizontal axis indicates a pixel which is
Mengistu Amare
NEC Corporation
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