Liquid crystal cells – elements and systems – Particular excitation of liquid crystal – Electrical excitation of liquid crystal
Reexamination Certificate
1998-09-25
2004-08-10
Parker, Kenneth (Department: 2871)
Liquid crystal cells, elements and systems
Particular excitation of liquid crystal
Electrical excitation of liquid crystal
C349S151000
Reexamination Certificate
active
06774957
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) and to a method for manufacturing such LCDs, and in particular to a peripheral driving circuit integrated LCD in which a thin film transistor (TFT) is used as a switching element in a display area and a driving circuit is formed around the display area, and a method for manufacturing the same. The manufacturing method of this invention prevents dielectric breakdown of an element due to static electricity generated in the manufacturing process.
2. Description of the Related Art
LCDs are commonly employed in office automation and audio visual apparatuses because of their advantageously small size, thin shape, and low power consumption. In particular, active matrix LCDs employing a TFT for a switching element to control writing of pixel information into pixels, are used for displays of various television sets or personal computers as they can precisely display motion pictures on a large screen.
A TFT is a field effect transistor (FET) made by forming metallic and semiconductor layers of a predetermined shape on a insulating substrate. In an active matrix LCD, the TFT is connected to the pixel electrodes for driving liquid crystal. Note that a common electrode, a pixel electrode, and liquid crystal sandwiched by these, together constitute a capacitor which corresponds to one pixel.
In recent years, an LCD has been developed which employs polysilicon (p-si) for the semiconductor layer, instead of amorphous silicon which was mainly used. Laser light is used to anneal, form, and grow p-Si crystal. In general, p-Si is superior in carrier movability to a-Si, and achieves TFT size reduction which enables formation of a highly precise, fine LCD with a higher opening rate. Moreover, when a gate self-align structure enables formation of a fine structure, and reduced parasitic capacitance enables high-speed processing, it is possible to form a high speed driving circuit through employment of an electric complementary structure which uses an n-ch TFT and a p-Ch TFT, i.e., CMOS. This further allows formation of a driving circuit around a pixel area on the same substrate, so that manufacturing costs and the size of an LCD module can be reduced.
Referring to
FIG. 11
, which is a plan view of a mother substrate
1
of the aforementioned driver-integrated LCD, the mother substrate
1
includes four active matrix substrates
2
which constitute electrode substrates of LCDs on one. On each active matrix substrate
2
, respective areas are reserved for formation of a display area at the center, gate driver
40
on the left and right sides thereof, a drain driver thereabove, a precharge driver
6
therebelow, an input terminal area
7
along the lower edge of the substrate
2
. The input terminal area
7
is connected to a flexible print connector (FPC), which is mounted with an integrated circuit for generating a control signal to be supplied via the FPC to the input terminal area
7
.
From the input terminal area
7
, a vertical clock pulse feeding wire
41
and a vertical start pulse feeding wire
42
extend to the gate driver
4
; a horizontal clock pulse feeding wire
51
, a horizontal start pulse feeding wire
52
, and a video data feeding wire
53
extend to the drain driver
5
; and a horizontal clock pulse feeding wire
61
and a horizontal start pulse feeding wire
62
extend to the precharge driver
6
.
After an opposing glass substrate is attached to the motor substrate
1
, the substrate
1
is cut along the break line
8
into four sheets of active matrix panels. Note that the opposing glass substrate has common electrodes formed thereon correspond to the substantial area of each active matrix substrate.
Referring to
FIG. 12
which is an enlarged plan view of an active matrix substrate
2
, a display area
3
is formed such that horizontally extending gate lines
31
intersect vertically extending drain lines
32
, and a switch element
33
is provided at each crossing, connected to the pixel electrode for driving crystal liquid.
A gate driver
4
mainly comprises a shift register for supplying a scanning signal voltage to the gate lines
31
in response to a vertical clock pulse. A drain driver
5
mainly comprises a shift register and a sampling gate for supplying a display signal voltage to the drain lines
32
in response to a horizontal clock pulse.
A precharge driver
6
, comprising mainly a shift register, is provided, when necessary, to supply the display signal voltage to the drain lines
32
earlier than the drain driver
5
to eliminate residual voltage in the drain lines
32
since previous scanning periods.
In the input terminal area
7
, input terminals
71
are arranged respectively connected to the wires
41
,
42
,
51
,
52
,
53
,
61
,
62
.
Each switch element
33
comprises, for example, a TFT, and all switch elements
33
in the same row are collectively turned on by a scanning signal voltage, in synchronism with which the display signal voltage is applied from the drain lines
32
to each pixel electrode
34
. By using the applied voltage as display information, permeability of liquid crystal in each pixel is controlled so as to display an image using bright and dark pixels.
A driver for the aforementioned driver-integrated LCD is made by forming a p-Si (polysilicon) TFT on a substrate. That is, a CMOS is formed using a pair of TFTs each having the same structure as that of a TFT used for a switch element
33
in the display area so that a number of inverter circuits are formed on a single substrate, forming respective drivers
4
,
5
,
6
.
Referring to
FIG. 13
, which is a cross sectional view of major elements of the aforementioned active matrix substrate
2
, from left to right in the drawing are shown a TFT area, a wire
41
,
42
,
52
,
52
,
53
,
61
,
61
area, and an input terminal
71
. On a glass substrate
100
, a gate electrode
101
and an input terminal pedestal
121
are formed as a first conductive layer made of Cr or the like. Above them, a gate insulating film
102
, a p-Si film
103
, an injection stopper
104
, an interlayer insulating film
105
, a source electrode
106
, a drain electrode
107
, a wire
116
, an input terminal
126
, a flattening insulating film
108
, a pixel electrode
109
, and an input terminal contact film
129
are formed. The source electrode
106
, the drain electrode
107
, the wire
116
, and the input terminal
126
are made of Al or the like to serve as a second conductive layer; the pixel electrode
109
and the input terminal contact film
129
are made of indium tin oxide (ITO).
As can be seen from this drawing, the input terminal
71
has a three-layer structure including an input terminal pedestal
121
, an input terminal
126
, and an input terminal contact film
129
. The input terminal
126
, integrated with the wire
116
, is made of a highly conductive Al or the like, which, however, is inferior in property of attaching to the substrate
100
. Therefore, an input terminal pedestal
121
made of Cr, which adheres well to both Al and glass, is provided as a base of the input terminal
126
to ensure rigid adherence between the input terminal
126
and the substrate
100
.
Because anisotropy conductive resin used as an adhesive member with an FPC is not easily used with the input terminal
126
, an input terminal contact film
129
made of ITO is intervened so as to ensure better adherence with the FTC.
First, a gate line
31
, a gate electrode
101
, and an input terminal pedestal
121
may be formed. That is, a gate electrode
101
for a switching element and a gate line
31
integrated with the gate electrode
101
are formed in the display area
3
; a gate electrode
101
for a CMOS TFT and lower wires for wire bonding are formed in the driver areas
4
,
5
,
6
; and a pedestal
121
for an input terminal
71
is formed in the input terminal area
7
. A source electrode
106
, a drain electrode
107
, drain lines
32
, and wires
41
,
42
,
51
,
52
,
53
are not yet formed.
A
Hirai Kyoko
Jinno Yushi
Hogan & Hartson LLP
Parker Kenneth
Sanyo Electric Co,. Ltd.
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