Computer graphics processing and selective visual display system – Display driving control circuitry
Reexamination Certificate
2007-01-30
2007-01-30
Hjerpe, Richard (Department: 2629)
Computer graphics processing and selective visual display system
Display driving control circuitry
C345S100000, C345S208000, C327S276000
Reexamination Certificate
active
10766218
ABSTRACT:
To prevent a timing shift of a clock and data supplied to a driver IC.A driver1011includes a phase adjustment circuit201for receiving via input terminals a clock and data outputted from a controller103, latching received data with the clock adjusted to a 50-percent duty ratio, and outputting as phase-adjusted signals the data having the latched data further latched by synchronizing it with a delay clock having the duty-ratio-adjusted clock delayed by (π/2) and the clock of the 50-percent duty ratio.
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Untranslated Office Action issued by Japanese Patent Office on Nov. 15, 2005 in in connection with corresponding Japanese application No. 2003-021080.
English translation of Japanese Office Action dated Nov. 15, 2005 issued in connection with corresponding Japanese application No. 2003-021080.
Japanese translation of Office Action issued by Korean Patent Office on Sep. 29, 2005 in connection with corresponding Korean application No. 10-2004-0004907.
English translation of Japanese translation of Nov. 22, 2005 Office Action issued in connection with corresponding Korean application No. 10-2004-0004907.
Untranslated Office Action issued by Korean Patent Office on Sep. 29, 2005 in connection with corresponding Korean appl. No. 10-2004-0004907.
Hjerpe Richard
NEC Electronics Corporation
Ostrolenk Faber Gerb & Soffen, LLP
Said Mansour M.
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