Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2001-10-12
2004-08-03
Chang, Kent (Department: 2673)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S087000
Reexamination Certificate
active
06771245
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a liquid crystal display apparatus driving method capable of preventing degradation in display quality of a liquid crystal display apparatus.
2. Description of the Related Art
A liquid crystal apparatus has power-consumption and portability advantages over other known image display apparatuses, and thus development in the liquid crystal apparatus field has been actively pursued.
FIG. 11
is a timing chart of voltage waveforms, illustrating a prior art TFT liquid crystal display apparatus driving method. In the figure, Line L
1
represents a waveform of a voltage applied to a pixel electrode; Line L
2
represents a waveform of a scanning voltage inputted to a gate electrode; Line L
3
represents a waveform of a display voltage inputted to a source electrode; Line L
4
represents a reference potential, i.e. an intermediate potential of the display voltage; and Line L
5
represents a counter potential of a common electrode.
When a positive gate-on voltage is applied to the gate electrode, the TFT is turned on, and thereby a display voltage is fed from the source electrode so as to be inputted via a drain electrode to the pixel electrode acting as a reflecting electrode. As a result, pixels are turned on. The TFT is kept in the ON state for a predetermined period of time, and, after a display voltage is applied to the pixel electrode, a gate-off voltage is applied to the gate electrode. Hereupon, the power supply to the pixel electrode is completed. The pixel electrode is, by exploiting the holding characteristics of the liquid crystal, maintained in a predetermined-voltage applied state until a gate-on voltage is applied once again to the TFT, i.e. over “gate-off” periods. When a gate-off voltage is applied to the gate electrode, due to subsequently-described parasitic capacitance Cgd, the voltage carried by the pixel electrode varies and takes a voltage variation value of &Dgr;V
1
calculated from the following formula:
&Dgr;
V
1
=&Dgr;
Vg×{Cgd
/(
Cgd+Clc+Ccs
)} (1)
Note that, in the above formula (1), &Dgr;V
1
represents a value of voltage variation resulting from the parasitic capacitance; &Dgr;Vg represents the displacement amount of the potential of the gate voltage (gate-on voltage relative to gate-off voltage); Cgd represents static capacitance of the parasitic capacitance; Clc represents static capacitance of liquid crystal capacitance; and Ccs represents static capacitance of hoplding capacitance.
Such voltage variation as occurs in the pixel electrode leads to a DC voltage component, and this DC voltage component acts upon a liquid crystal layer. The action of the DC voltage component exerted on the liquid crystal layer causes the liquid crystal to exhibit polarization, which results in degradation in the reliability of the liquid crystal. As a result, the display surface suffers from an image persistence. Hereinafter, a DC voltage component resulting from voltage variation occurring in the pixel electrode is referred to as the first DC voltage component &Dgr;V
1
.
To prevent the first DC voltage component &Dgr;V
1
from acting upon the liquid crystal layer, in the prior art, the circuit configuration of the liquid crystal display apparatus is designed such that the first DC voltage component &Dgr;V
1
calculated from the formula (1) is corrected beforehand. In other words, the potential of the common electrode to which a counter electrode is connected standing at the reference potential (i.e. the intermediate potential of the display voltage indicated by the line L
4
) level is shifted by an amount of the first DC voltage component &Dgr;V
1
in a negative potential direction so as to be initially set at the counter potential level indicated by Line L
5
.
Voltage variation resulting from the parasitic capacitance Cgd is possibly suppressed by adopting such a power source circuit configuration as shown in FIG.
12
. In this case, Hi-voltage and Low-voltage are outputted in response to a control signal Vin at given intervals. When High-voltage is fed, a switch S is turned on, and thereby a voltage of a power source P
1
is applied to a capacitor C. After a lapse of a predetermined period of time, Low-voltage is outputted in response to the control signal Vin, and thereby a GND (ground) potential is applied to the capacitor C. By applying to the capacitor C a power source voltage and a GND voltage at predetermined intervals, an alternating voltage is outputted from the capacitor C to the common electrode side (output signal: Vout). Then, a specific voltage is applied to the alternating voltage so that the voltage variation resulting from the parasitic capacitance Cgd of the capacitor C is corrected.
An application voltage refers to a voltage which is outputted from a power source P
2
and is then fed toward a resistance R
3
side through divided resistance, i.e. resistances R
1
and R
2
.
FIG. 13
shows a waveform of the output signal Vout. The waveform of the output signal Vout is formed as a composite waveform created by linking the waveform of the alternating voltage from the capacitor C and the waveform of the DC voltage from the power source P
2
. By applying a correction voltage to the common-electrode side in that way, the influence of the voltage variation resulting from the parasitic capacitance Cgd can be suppressed.
However, application of a correction voltage requires an additional power source, like the power source P
2
shown in FIG.
12
. In addition, a negative power source is required for correcting the alternating voltage of the common electrode. This leads to an undesirable increase of power consumption.
A DC voltage component acting upon the liquid crystal layer is caused not only by the above-described parasitic capacitance Cgd but also by asymmetricity in characteristics between an active matrix substrate and a counter substrate that have sandwiched therebetween the liquid crystal layer. A DC voltage component resulting from the asymmetricity between the active matrix substrate and the counter substrate acts upon the liquid crystal layer constantly. Hereinafter, a DC voltage component resulting from the difference in characteristics between the mutually-opposing substrates is referred to as the second DC voltage component &Dgr;V
2
.
The asymmetricity in characteristics between the substrates includes: the difference in thickness between the active-matrix-substrate-side alignment film and the counter-substrate-side alignment film; the difference in material between the active-matrix-substrate-side alignment film and the counter-substrate-side alignment film (observed in the case of hybrid orientation); and the difference in material between two electrodes opposed to each other with a liquid crystal layer therebetween, like an Al-made active-matrix-substrate-side reflecting electrode and an ITO-made counter-substrate-side transparent electrode in a reflection-type liquid crystal display apparatus. Of these factors, in particular, the asymmetricity defined by the difference in material between electrodes opposed to each other with a liquid crystal layer therebetween causes the largest second DC voltage component &Dgr;V
2
.
Moreover, the second DC voltage component &Dgr;V
2
resulting from the difference in material between the electrodes cannot be obtained by calculation. Therefore, it takes much time to adjust the potential of the common electrode properly, and, during the adjustment, the second DC voltage component &Dgr;V
2
continues to act upon the liquid crystal layer. This leads to degradation in the reliability of the liquid crystal display apparatus and causes problems such as occurrence of an image persistence.
Further, Japanese Unexamined Patent Publication JP-A 2-64525 (1990) discloses a technique for preventing occurrence of the second DC voltage component &Dgr;V
2
by making the active-matrix-substrate-side alignment film identical in material and thickness with the counter-substrate-side alignment film. Howe
Fujiwara Sayuri
Kanbe Makoto
Tsuda Kazuhiko
Chang Kent
Conlin David G.
Edwards & Angell LLP
Sharp Kabushiki Kaisha
Sheng Tommy
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