Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
1998-03-25
2004-05-04
Hjerpe, Richard (Department: 2674)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S095000, C345S098000
Reexamination Certificate
active
06731265
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a display apparatus and a method for driving the same, and more particularly to a display apparatus such as a liquid crystal display apparatus, for example, used for audio visual (AV) equipment, office automation (OA), etc., which uses a voltage generating device forming a part of a driving device and a method for driving the same.
2. Description of the Related Art
FIG. 23
shows an example of the liquid crystal display apparatus as described above. The liquid crystal display apparatus includes a display panel
1001
which performs a display function, a scanning electrode signal driver
1002
for applying a predetermined voltage to scanning electrode lines Y
1
to Y
m
of the display panel
1001
in a line sequence, and a data electrode signal driver
1003
for applying a predetermined voltage to data electrode lines X
1
to X
n
of the display panel
1001
in accordance with display information. In addition, the apparatus includes a voltage generating section
1006
for generating a voltage applied to the scanning electrode signal driver
1002
and the data electrode signal driver
1003
, and a control section
1005
which receives information from an input signal line
1004
to send a control signal to the scanning electrode signal driver
1002
, the data electrode signal driver
1003
, and the voltage generating section
1006
, respectively.
The voltage generating section
1006
includes a data signal voltage generating circuit
1101
, a non-selection voltage generating circuit
1102
, and a write voltage generating circuit
1103
, as shown in FIG.
24
.
The voltage generating section
1006
receives a logic circuit power-supply voltage V
cc
, a supply voltage V
ee
, and a control signal S
d
. Alternatively, the supply voltage V
ee
may not be input to the voltage generating section
1006
; in such a case, a supply voltage is generated by a booster circuit, etc. in the voltage generating section
1006
based on the logic circuit power-supply voltage V
cc
. The voltage generating section
1006
generates a data signal voltage VD, a non-selection voltage VM, a positive electrode side write voltage VH, and a negative electrode side write voltage VL based on input signals such as the logic circuit power-supply voltage V
cc
, the supply voltage V
ee
, and the control signal S
d
.
The data signal voltage VD, the non-selection voltage VM, and the write voltages VH and VL satisfy the following Expressions (1) and (2):
VD=
2
×VM
(1)
|VL|=|VH|−|VD|
(2)
As shown in
FIG. 21
, the display panel
1101
has a simple matrix type structure in which pixels are arranged in a matrix. Each pixel is composed of one of the scanning electrode lines Y
1
to Y
m
, one of the data electrode lines X
1
to X
n
, and the liquid crystal
1201
provided between the electrode lines.
Referring back to prior art
FIG. 23
, the scanning electrode signal driver
1002
is composed of a shift register, an analog switch, etc., and the data electrode signal driver
1003
is composed of a shift register, a latch circuit, an analog switch, etc.
FIG. 25
shows an exemplary operation of the scanning electrode signal driver
1002
. It is noted that the scanning electrode signal driver
1002
applies a predetermined voltage to the scanning electrode lines Y
1
to Y
m
in accordance with a latch pulse LP and an alternating signal M.
The scanning electrode signal driver
1002
receives a scanning commencement signal S (not shown), the latch pulse LP, the alternating signal M, and various voltages
1305
(i.e., the write voltages VH and VL, the non-selection voltage VM, and a reference voltage VS) from the control section
1005
. The reference voltage VS is generally 0 volt, so that it may be omitted hereinafter. The scanning electrode signal driver
1002
applies the positive electrode side write voltage VH or the negative electrode side write voltage VL supplied from the voltage generating section
1006
to a selected line during a selection period, and the non-selection voltage VM to the selected line during a non-selection period.
Furthermore,
FIG. 25
shows waveforms
1306
and
1307
of voltages applied to the scanning electrode lines Y
i
and Y
i+1
. As represented by the waveform
1306
, during a selection period
1303
in an A frame
1301
, the write voltage VH is applied to the scanning electrode line Y
i
in accordance with the latch pulse LP and the alternating signal M. During a selection period
1304
in a B frame
1302
, the write voltage VL is applied to the scanning electrode line Y
i
in accordance with the latch pulse LP and the alternating signal M, and during a non-selection period, the non-selection voltage VM is applied to the scanning electrode line Y
i
. On the other hand, as represented by the waveform
1307
, during a selection period
1308
in the A frame
1301
, the write voltage VL is applied to the scanning electrode line Y
i+1
in accordance with the latch pulse LP and the alternating signal M. During a selection period
1309
in the B frame
1302
, the write voltage VH is applied to the scanning electrode line Y
i+1
, and during the non-selection period, the non-selection voltage VM is applied to the scanning electrode line Y
i+1
in accordance with the latch pulse LP and the alternating signal M. Herein, the A+B frames each refer to one period of the scanning commencement signal S, and the non-selection period refers to a period obtained by excluding the selection periods from one frame.
FIG. 26
shows signals which are transmitted to the data electrode signal driver
1003
. The data electrode signal driver
1003
receives the latch pulse LP, the alternating signal M, a data signal D, and a data transfer clock signal CLK from the control section
1005
. Data of each data electrode line X
j
is determined based on the data signal D and the data transfer clock signal CLK.
FIG. 27
shows an exemplary operation of the data electrode signal driver
1003
. The data electrode signal driver
1003
receives the data signal voltage VD, the non-selection voltage VM, and the reference voltage VS, in addition to the above-mentioned signals, from the voltage generating section
1006
.
The data electrode signal driver
1003
applies the latch pulse LP, the alternating signal M, and the data signal transmitted from the control section
1005
and the data signal voltage VD or the reference voltage VS transmitted from the voltage generating section
1006
to a selected line. For example, in the case where data DX
j
of the data electrode line X
j
is at a high level as represented by reference numeral
1509
, the data electrode line X
j
is supplied with a voltage represented by a waveform
1506
in accordance with the latch pulse LP and the alternating signal M. Reference numeral
1507
shows a waveform of a voltage applied to the scanning electrode line Y
i
. Thus, a waveform applied to a pixel at a coordinate (X
j
, Y
i
) is as represented by reference numeral
1508
.
In a general liquid crystal display apparatus, the data signal voltage VD is constant irrespective of an ambient temperature or the like, as shown in FIG.
27
.
FIG. 28
shows contrast-supply voltage characteristics at each temperature when the data signal voltage VD is constant.
In
FIG. 28
, a curve
1603
represents a contrast-supply voltage characteristic at T
a
=0° C., where T
a
is a temperature of a liquid crystal display apparatus; a curve
1602
represents a contrast-supply voltage characteristic at T
a
=25° C.; and a curve
1601
represents a contrast-supply voltage characteristic at T
a
=50° C.
As is understood from
FIG. 28
, if a use temperature of the liquid crystal display apparatus is in a range of 0° C. to 50° C., it is required to vary a supply voltage for the liquid crystal driving circuit between V
a1
and V
c1
in order to improve the contrast of the apparatus. Furthermore, in the case where the
Kokuhata Yoshiyuki
Takahashi Masahiro
Dinh Duc Q
Hjerpe Richard
Nixon & Vanderhye PC
Sharp Kabushiki Kaisha
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