Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2008-03-12
2011-10-25
Lao, Lun-Yi (Department: 2629)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S080000, C345S204000, C345S082000, C315S169300, C313S463000, C313S509000, C377S063000, C377S067000, C377S069000
Reexamination Certificate
active
08044894
ABSTRACT:
After a sampling transistor is turned ON at a first timing when a control signal has risen, during a sampling period from a second timing when a video signal has risen from a reference potential to a signal potential to a third timing when the control signal has fallen and is turned OFF, the sampling transistor samples and writes the signal potential in a holding capacitance, and negatively feeds back a current flowing into a drive transistor during the sampling period to the holding capacitance and applies mobility correction of the drive transistor on the written signal potential. A signal driver adjusts the second timing for the video signal supplied to respective signal lines to correct a backward shift of the third timing due to a transmission delay along a scanning line of the control signal output from the control scanner.
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Japanese Office Action issued Mar. 17, 2009 for corresponding Japanese Application No. 2007-074986.
Uchino Katsuhide
Yamamoto Tetsuro
Lao Lun-Yi
Merkoulova Olga
Rader & Fishman & Grauer, PLLC
Sony Corporation
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