Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2001-09-20
2004-09-14
Lao, Lun-Yi (Department: 2673)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S087000, C345S094000, C345S204000
Reexamination Certificate
active
06791525
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a display apparatus and driving method for the same. More particularly, the present invention is suitably applied to a liquid crystal display apparatus.
FIG. 6
is an explanatory view showing a construction of a conventional liquid crystal display apparatus. In
FIG. 6
, reference numeral
20
indicates a liquid crystal panel serving as a display means,
21
denotes a scanning line driving circuit for driving scanning lines,
22
denotes a signal line driving circuit for driving signal lines,
23
denotes a control circuit for controlling input signals inputted to the scanning line control circuit, the signal line control circuit and the like, and
24
denotes a power supply section for generating the reference voltages of the driving circuits
21
and
22
.
With the electrical circuit configuration of the display apparatus such as a liquid crystal display apparatus, external input signals (the input signal of the control circuit
23
) involve a clock input signal, an image data signal, a data enable input signal and the other control input signals (e.g., a horizontal synchronizing input signal and a vertical synchronizing input signal). Here, the data enable input signal defines the effective data period of the image data signal with respect to a time axis. Normally, the data enable input signal has a High voltage level in the effective data period and has a Low voltage level in periods other than the effective data period.
FIG. 7
is the graph showing a voltage of signals inputted into the control circuit
23
per horizontal cycle. In
FIG. 7
, horizontal axis direction represents a time axis, reference numeral
51
denotes a horizontal synchronizing input signal voltage,
52
denotes a data enable input signal voltage,
53
denotes a clock input signal voltage,
54
denotes an image data signal voltage, 1CLK denotes the cycle of a clock input signal and 1H denotes the cycle of the horizontal synchronizing signal. Also, an arrow at each edge of the clock input signal
53
denotes the active edge of the clock input signal (in case of
FIG. 7
, a falling edge is used as the active edge), D denotes the effective data period of the image data signal, the blank portion (that is, portion without hatching) of the image data signal voltage
54
corresponds to the effective data period and portions other than the blank portion (that is, hatched portion) of the image data signal voltage
54
corresponds to the ineffective data periods of the image data signal. Numerals
1
,
2
,
3
, . . . , m corresponds to frame size (in other word, resolution or pixels) in horizontal direction. It is assumed herein that the Low voltage level of the horizontal synchronizing input signal indicates a reset period, meaning that no effective data period exists.
FIG. 8
is a voltage waveform view of signals inputted into the control circuit
23
per vertical cycle. In
FIG. 8
, horizontal axis direction represents a time axis, reference numeral
55
denotes a vertical synchronizing input signal voltage, reference numeral
52
denotes a data enable input signal voltage, reference numeral
54
denotes an image data signal voltage, 1H denotes the cycle of the horizontal synchronizing input signal, 1V denotes the cycle of the vertical synchronizing input signal and D denotes the effective data period of the image data signal. Also, the blank portion (un-hatched portion) of the image data signal voltage
54
denotes the effective data period of the image data signal and portions other than the blank portions (hatched portion) denote ineffective data periods. Numerals
1
,
2
,
3
, . . . , n denote frame size (resolutions or pixels) in vertical direction. It is assumed herein that the Low voltage level of the vertical synchronizing input signal indicates a reset period, meaning that no effective data period exists.
Further, as the output signals of the control circuit
23
, clock signals and data signals are generated to be used as input signals inputted into the driving circuit
21
and
22
generating signals driving the liquid crystal panel
20
. It is assumed herein that the clock signals represent clock signals used in the respective driving circuits
21
and
22
(i.e., a vertical clock signal for the scanning line driving circuit
21
and a horizontal clock signal for the signal line driving circuit
22
). In addition, it is assumed that the data signals represent an image data signal (or horizontal image data output signal), control signals other than the image data signal (e.g., a horizontal start output signal, a vertical start output signal, a horizontal latch output signal and a horizontal driving voltage polarity control output signal) or the like.
In connection with a method of driving the ordinary liquid crystal display apparatus as stated above, a liquid crystal display apparatus disclosed in Japanese Patent No. 2,616,652 is shown in
FIG. 9
as a conventional technique making it possible to realize the high-speed response of a liquid crystal. In
FIG. 9
, reference numeral
25
denotes a television antenna, reference numeral
26
denotes a tuner, reference numeral
27
denotes a television linear circuit, reference numeral
28
denotes a synchronous control circuit, reference numeral
29
denotes an A/D conversion circuit, reference numeral
30
denotes a common electrode driving circuit,
31
denotes an image memory capable of storing one-frame image data, reference numeral
32
denotes a comparison circuit and reference numeral
33
denotes a segment electrode driving circuit.
In the liquid crystal display apparatus constituted as shown in
FIG. 9
, the comparison circuit
32
compares the level of image data outputted from the A/D conversion circuit
29
and the level of image data read from the image memory
31
one frame later than the image data outputted from the A/D conversion circuit
29
. If the present image data is higher in level than the one-frame-prior image data, the comparison circuit
32
outputs a maximum value “7”, i.e., “111” as image data D
1
to D
3
and outputs “1” as a gradation change signal. Further, if the one-frame-prior image data is equal in level to the present image data, the comparison circuit
32
outputs the image data fed from the A/D conversion circuit
29
as image data D
1
to D
3
as they are and outputs “0” as a gradation change signal. Further, if the present image data is lower in level than the one-frame-prior image data, the comparison circuit
33
outputs a minimum value “0”, i.e., “000” as image data D
1
to D
3
and outputs “1” as a gradation change signal.
As a result of the comparison, if the present image data is higher in level than the one-frame-prior image data, the segment electrode driving signal is controlled to have high amplitude, i.e., to have high voltage, whereby the light transmittance of the liquid crystal panel
20
rises faster than that in case of the conventional driving method. Further, if the one-frame-prior image data is equal in level to the present image data, ordinary liquid crystal driving voltage is applied to the liquid crystal panel. If the present image data is lower in level than the one-frame-prior image data, the liquid crystal driving voltage is set lower than the ordinary voltage value, whereby the light transmittance of the liquid crystal panel
20
is lowered faster than that in case of the conventional driving method.
FIG. 10
shows the relationship among image data signal (a), liquid crystal driving voltage (b) and transmittance (c) in the liquid crystal display apparatus constituted as shown in
FIG. 9
, while the horizontal axis is a time axis. In
FIG. 10
, reference numeral
8
denotes a liquid crystal driving voltage shown in the above-cited reference (Japanese Patent No. 2,616,652),
34
denotes ordinary liquid crystal driving voltage of former technique,
10
denotes transmittance attained with the driving voltage
8
and
35
denotes ordinary transmittance attained with the driving voltage
34
. In
FIG. 10
, if the ordinary liquid crys
Matsumura Tatsuya
Shibata Susumu
Advanced Display Inc.
Lao Lun-Yi
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
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