Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2010-09-20
2011-11-08
Sherman, Stephen (Department: 2629)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C377S064000, C345S204000
Reexamination Certificate
active
08054278
ABSTRACT:
There is a need for decreasing a variation in times for writing to TFT elements for pixels in a direction along the extension of a gate line in a liquid crystal display apparatus. A display apparatus includes a display panel having multiple gate lines and multiple drain lines arranged in a matrix and a data driver for outputting a display data signal to each drain line. The data driver includes: an internal control signal generation circuit for generating an internal control signal for setting a timing to output a data signal to a drain line of each block on a block basis by dividing the plurality of drain lines into multiple blocks; and a register circuit for recording a setting for division of the block, a setting for a delay direction and a delay width of a timing to output the data signal, and a setting for rising and falling of an internal control signal.
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Iida Haruhisa
Isami Hironobu
Kikuchi Hidenori
Ode Yukihide
Tanaka Yasuhiro
A. Marquez, Esq. Juan Carlos
Hitachi Displays Ltd.
Sherman Stephen
Stites & Harbison PLLC
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