Computer graphics processing and selective visual display system – Display driving control circuitry – Waveform generator coupled to display elements
Reexamination Certificate
1999-09-15
2002-10-29
Saras, Steven (Department: 2675)
Computer graphics processing and selective visual display system
Display driving control circuitry
Waveform generator coupled to display elements
C345S092000, C345S100000
Reexamination Certificate
active
06473077
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a display apparatus, such as a liquid crystal display (LCD) device, a plasma display device, a field emission display device, with a high response speed which can prevent the display image from becoming unclear due to an overlap of the afterimage of the display image of the preceding frame period with the display image of the current frame period to improve the image quality of the motion picture.
2. Discussion of the Related Art
The LCD device with the high response speed, such as a Bend-mode LCD device well known in the art, has been used for improving the image quality of the motion picture in which the displayed image is changed at a high speed. Describing problems in the high response speed LCD device with reference to FIGS.
1
(A) and (B), the FIG.
1
(A) shows a schematic configuration of a prior LCD device, which includes a LCD array
1
, a data line drive circuit
2
and a gate line drive circuit
3
. For example, the LCD array
1
has 640×480 pixels of VGA (Video Graphic Array) scheme. In this case, the data line drive circuit
2
supplies the image data to the 640 data lines connected to the 640 pixels of one pixel line, respectively, and the gate line drive circuit
3
sequentially supplies a gate pulse to the 480 gate lines. More particularly, when the data are written into a first pixel line along the gate line G
1
, the image data for the 640 pixels of the first pixel line stored in the data line drive circuit
2
are supplied to the data lines, and the gate line drive circuit
3
supplies the gate pulse to the gate line G
1
. The gate pulse turns on a thin film transistor of each pixel of the first pixel line, so that the image data are stored in a capacitor of each pixel formed by a pixel electrode, a liquid crystal layer and a common electrode, as well known in the art. When the data are written into a second pixel line along the gate line G
2
, the image data for the 640 pixels of the second pixel line stored in the data line drive circuit
2
are supplied to the data lines, and the gate line drive circuit
3
supplies the gate pulse to the gate line G
2
, and so on.
The FIG.
1
(B) shows a timing diagram for sequentially supplying of the gate pulses to the 480 gate lines. During one frame period, the gate pulses are sequentially supplied to the 480 gate lines, so that the image data are sequentially written into the pixel lines during one frame period, as shown in the FIG.
1
(B). A blanking period is provided between the adjacent two frame periods. The gate pulse has a width represented by a time period TA, which is represented by (the length of the frame period)/(the number of the gate lines). The time period TA is designed to turn on the thin film transistor of each pixel for sufficiently writing the image data into the capacitance of each pixel.
A problem in this scheme is that when the displayed image is changed for each frame period to display the motion picture, the displayed image of the one frame period remains in the human eyes as an afterimage and this afterimage overlaps with the display image of the next frame period, so that the image quality of the displayed image is degraded.
FIG. 2
shows a timing diagram of a prior scheme for solving the problem of the afterimage caused in the scheme shown in the FIG.
1
. One frame period is divided into a ½ frame period A and a ½ frame period B. During the first ½ frame period A, the 480 gate lines are sequentially activated to write the image data into all the pixel lines of the LCD array, and during the second ½ frame period B, the 480 gate lines are sequentially activated to write the black data into all the pixel lines of the LCD array. This operation can be performed by modifying the control scheme of the LCD device shown in the FIG.
1
(A). Describing the write operation in the second ½ frame period B, when the black data are written into the first pixel line along the gate line G
1
, the black data for the 640 pixels of the first pixel line are stored in the data line drive circuit
2
, and the gate line drive circuit
3
supplies the gate pulse to the gate line G
1
. The gate pulse turns on a thin film transistor of each pixel of the first pixel line, so that the black data are stored in the capacitance of each pixel. When the black data are written into the second pixel line along the gate line G
2
, the black data for the 640 pixels of the second pixel line are stored in the data line drive circuit
2
, and the gate line drive circuit
3
supplies the gate pulse to the gate line G
2
, and so on. In this manner, the human eyes recognize the black image during the second ½ period B, and the afterimage of the image displayed in the first ½ period A is deleted from the human eyes during the ½ frame period B and is not overlap with the image of the next frame period. Although this scheme solves the problem of the afterimage, this scheme causes a new problem that the width of the gate pulse is reduced into TA/2, since the number of gate pulses twice as much as that of the FIG.
1
(B) is required during one frame period, so that image data is not sufficiently written into the capacitance of the pixel, whereby the sufficient control of gray scale is not performed.
FIG. 3
shows a prior LCD device for solving the problem in the scheme shown in the FIG.
2
. The LCD array is divided into a LCD array A which includes the gate lines G
1
through G
240
and a LCD array B which includes the gate lines G
241
through G
480
, and the data line drive circuit
4
is used to supply the data to the LCD array A and the data line drive circuit
5
is used to supply the data to the LCD array B. The FIG.
3
(B) shows a timing diagram of the operation of the LCD device. One frame period is divided into a ½ frame period A and a ½ frame period B. During the ½ frame period A of the first frame period, the 240 gate lines of the LCD array A are sequentially activated to write the image data into all the pixel lines of the LCD array A. During the ½ frame period B of the first frame period, the 240 gate lines of the LCD array A are sequentially activated to write the black data into all the pixel lines of the LCD array A, and the 240 gate lines of the LCD array B are sequentially activated to write the image data into all the pixel lines of the LCD array B. The black data for the LCD array B, into which the image data are written during the first frame period, are written in the ½ frame period A of the next frame period.
Since the LCD array is divided into the two halves, the write operation of the image data and the black data into the upper half A and the lower half B can be independently performed from each other, the width of the gate pulse can be maintained to the TA for sufficiently write the image data or the black data into the capacitance of each pixel, whereby this scheme solves the problem in the scheme shown in the FIG.
2
. However, this scheme causes a new problem that this scheme requires the division of the LCD array into the two halves and the two data line drive circuits
4
and
5
, so that the complicated control for supplying the data into the data line drive circuits
4
and
5
is required and the fabrication cost is increased.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide the display apparatus which can prevent the display image from becoming unclear due to an overlap of the afterimage of the display image of the preceding frame period with the display image of the current frame period to improve the image quality of the motion picture, without requiring the division of the LCD array into the two halves and the two data line drive circuits.
In a first aspect of the present invention, a display apparatus in accordance with the present invention includes:
a display surface having a plurality of pixel lines; and a write circuit adapted to sequentially write an image into each of
Ikezaki Mitsuru
Takenaka Atsushi
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