Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2000-12-18
2003-05-27
Mengistu, Amare (Department: 2873)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S209000
Reexamination Certificate
active
06570553
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a display and its driving method and, more particularly, to a display for inputting an image signal of an AC voltage to each pixel and its driving method.
2. Related Background Art
In recent years, multimedia has become increasingly important and the amount of information that is handled in society has rapidly increased. In such a situation, in place of a CRT (Cathode Ray Tube), a thin type flat display as an interface from a computer to a human being has become an important device to widen the multimedia market. As flat displays, LCD (liquid crystal display), PDP (plasma display), and an electron beam flat displays are leading devices. Among them, the liquid crystal display is achieving a wider market in association with a widespread use of small personal computers. Among the liquid crystal displays, active matrix liquid crystal display has no crosstalk as compared with a simple matrix liquid crystal display of an STN (super twisted nematic) type or the like, so that the active matrix LCD has a large contrast over the whole picture plane. Such an active matrix LCD is, therefore, has attracted use as not only a display of the small type personal computer but also for use as a view finder of a video camera, a projector, and a thin type television.
Among active matrix liquid crystal displays there are TFT (thin film transistor) type displays and diode type displays.
FIG. 10A
is a block diagram of an image signal input of a TFT type image display. Reference numeral
10
denotes an image pixel section having pixels arranged in a matrix shape;
20
a vertical scanning circuit for selecting a display row;
30
a sampling circuit of a color image signal; and
40
a horizontal scanning circuit for generating a signal of the sampling circuit.
A unit pixel of the display pixel section
10
comprises a switching element
11
, a liquid crystal material
15
, and a pixel capacitor
12
. In the case where the switching element
11
is a TFT (thin film transistor), a gate line
13
connects a gate electrode of the TFT and the vertical scanning circuit
20
. A common electrode
21
of an opposite substrate commonly connects terminals of one side of the pixel capacitor
12
of all of the pixels. A common electrode voltage V
LC
is applied to the common electrode
21
. When the switching element
11
is a diode (including a metal/insulator/metal element), a scan electrode is arranged in the lateral direction on the opposite substrate and is connected to the vertical scanning circuit
20
. An input terminal of the switching element
11
is connected to the sampling circuit
30
by a data line
14
in the vertical direction. In the case where the switching element
11
is any one of the TFT and the diode, the vertical direction data line
14
connects the input terminal of the switching element
11
and the sampling circuit
30
. An output terminal of the switching element
11
is connected to another terminal of the pixel capacitor
12
.
A control circuit
60
separates an image signal to signals necessary to the vertical scanning circuit
20
, horizontal scanning circuit
40
, a signal processing circuit
50
, and the like. The signal processing circuit
50
executes a gamma process considering liquid crystal characteristics, an inverting signal process to realize long life of the liquid crystal, and the like and generates color image signals (red, blue, and green) to the sampling circuit
30
.
FIG. 10B
is a detailed equivalent circuit diagram of the color-display pixel section
10
of the TFT type and the sampling circuit
30
. The pixels (R, G, B) are arranged in a delta shape and the pixels of the same color are distributed to both sides of the data lines
14
(d
1
, d
2
, . . . ) every row and are connected to the data lines (d
1
, d
2
, . . . ). The sampling circuit
30
is constructed by switching transistors (sw
1
, sw
2
, . . . ) and a capacitor (a parasitic capacitance of the data lines
14
and a pixel capacitance). An image signal input line
16
is constructed by signal lines only for R, G, B colors. The switching transistors (sw
1
, sw
2
, . . . ) sample the color signals of the image signal input line
16
in accordance with pulses (h
1
, h
2
, . . . ) from the horizontal scanning circuit
40
and transfer the color signals to the pixels through the data lines
14
(d
1
, d
2
, . . . ). Pulses (&phgr;g
1
, &phgr;g
2
, . . . ) are transmitted from the vertical scanning circuit
20
to TFT gates of the pixels and rows are selected, thereby writing the signals to the pixels. As mentioned above, the pulses (&phgr;g
1
, &phgr;g
2
, . . . ) turn on the TFTs
11
included in the rows, so that an image signal of one horizontal scan of each corresponding row is written to all of the pixels included in the rows. The image signal of one horizontal scan is called a 1H signal hereinbelow.
FIG. 11A
shows an example of an interlace scan of a liquid crystal display having rows of the same number as that of the vertical scanning lines of an image signal for a CRT type television based on the NTSC or the like. In the liquid crystal display, when the 1H signal is written to two rows, to decrease flickering of a moving image, 2-row simultaneous driving or a 2-row interpolation driving (signal writing corresponding to the pixels arranged in a delta shape) which is treated similarly to the 2-row simultaneous driving, is often executed. In those driving methods, a combination of two rows to be selected is changed in accordance with the odd field and the even field. In the following description, it is assumed that the rows on the display pixel section which are selected and to which information is written are designated by symbols (g
1
, g
2
, . . . ) of vertical scanning pulses. In the odd field, the 1H signal of a horizontal scan line odd
1
is written to the rows g
2
and g
3
. Similarly, the 1H signal of odd
2
is written to the rows g
4
and g
5
. Each of the 1H signals of odd
3
and subsequent horizontal scan lines is also similarly written for every two rows. On the other hand, in the even field, a combination of rows to be selected is deviated from the odd field by one row and the 1H signal of a horizontal scan line even
1
is written to the rows g
1
and g
2
. Similarly, the 1H signal of even
2
is written to the rows g
3
and g
4
and each of the subsequent signals is also similarly written for every two rows.
FIG. 12
shows a timing chart of scan pulses of the 2-row simultaneous driving. In the odd field, the vertical scan pulses fg
2
and fg
3
are set to the “H” level. The TFT corresponding to each of the pixels of the rows is turned on, thereby writing the 1H signal of odd
1
to the rows g
2
and g
3
. In this instance, for the “H” period of the horizontal scan pulses (h
1
, h
2
, . . . ), the image signal sampled by the sampling circuit is written to the pixels of the rows g
2
and g
3
. A similar writing operation is also executed in the scan of odd
2
and subsequent lines.
FIG. 11B
shows an example of the interlace scan of a liquid crystal display having rows of the number that is ½ of the number of vertical scan lines of the image signal for the CRT type television based on the NTSC or the like. In this case, the rows to be selected on the display pixel section are also shown by the symbols (g
1
, g
3
, . . . ) of the horizontal scan pulses. In the odd and even fields, the 1H signal is written to the same row. In the odd field, the 1H signal of the horizontal scan line odd
1
is written to the row g
2
and the 1H signal of odd
2
is written to the row g
4
. Similarly, each of the 1H signals of odd
3
and subsequent lines is also written. In the even field as well, the 1H signal of even
1
is written to the row g
2
and the 1H signal of even
2
is written to the row g
4
. Each of the subsequent signals is also similarly written by using rows (g
4
, g
8
, . . . ) to which the information was written in the odd field. A timing chart of the scan pulse shows a scan by the 2-row simultaneous dr
Hashimoto Seiji
Yoshida Daisuke
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