Semiconductor device manufacturing: process – Making device or circuit emissive of nonelectrical signal – Including integrally formed optical element
Reexamination Certificate
2002-09-30
2004-06-08
Zarabian, Amir (Department: 2822)
Semiconductor device manufacturing: process
Making device or circuit emissive of nonelectrical signal
Including integrally formed optical element
C438S149000, C438S152000, C438S609000, C438S622000, C438S632000, C438S633000, C438S692000, C438S698000, C438S699000, C438S782000
Reexamination Certificate
active
06746888
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a display and a fabrication method thereof. In particular, the present invention is suitably applied to a liquid crystal display of a type in which a conductive shield film is provided at a position over a thin film transistor for driving a pixel electrode and under the pixel electrode.
Liquid crystal displays have been extensively used as flat displays. As thin film transistors (TFTs) for driving pixel electrodes provided in these liquid crystal displays, amorphous silicon (a-Si) TFTs have been conventionally used; however, recently, polycrystalline Si TFTs have come to be frequently used. The optical sensitivity of a polycrystalline Si TFT is not higher than that of an a-Si TFT; however, since recent liquid crystal-displays, for example, projectors have been increasingly used under a large light quantity, even a polycrystalline Si TFT causes a non-negligible amount of light leakage current. The light leakage current leads to degradation of an image quality, such as reduction in contrast, crosstalk, or flicker.
To suppress the occurrence of a light leakage current from a thin film transistor of a liquid crystal display, there has been adopted a configuration in which the thin film transistor is covered with a shield film made from a metal. In general, the shield film is formed on the thin film transistor via an underlying insulating film, and a pixel electrode is formed on the metal made shield film via another insulating film. However, since the surface of the thin film transistor has irregularities, the shield film is affected by the irregularities of the thin film transistor via the insulating film. In particular, portions of the shield film, positioned at slopes of the irregularities of the thin film transistor, become thinner. The shielding performance of these thinner portions of the shield film becomes poor. Further, steps of the shield film, which are formed by the irregularities of the thin film transistor, also exert adverse effect on the surface of the insulating film on which the pixel electrode is to be formed. The surface of the insulating film on which the pixel electrode is formed is in contact with a liquid crystal, and in general, an alignment film is formed on the insulating film to cover the pixel electrode. As a result, if steps occurs on the surface of the insulating film by the effect of the steps of the shield film, it is difficult to uniformly treat an alignment film, which is formed on-the insulating film to cover the pixel electrode, over the entire surface of the substrate.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a display capable of improving both the shielding performance and the alignment characteristic, and a method of fabricating the display.
To achieve the above object, according to the present invention, there is provided a display in which a thin film transistor for driving a pixel electrode is provided on a substrate and a conductive shield layer is provided at a position over the thin film transistor and under the pixel electrode, the display including: a first planarization film formed to bury an irregular contour of the thin film transistor, the shield layer being disposed on the planarized surface of the first planarization film; and a second planarization film formed to bury steps of the shield layer, the pixel electrode being disposed on the planarized surface of the second planarization film. The first planarization film may be obtained by forming an insulating film, and planarizing the surface of the insulating film by chemical-mechanical polishing. The first planarization film may be obtained by smoothly applying an insulating material by spin-coating, and baking the insulating material. The second planarization film may be obtained by forming an insulating film, and planarizing the surface of the insulating film by chemical-mechanical polishing. The second planarization film may be obtained by smoothly applying an insulating material by spin-coating, and baking the insulating material. The second planarization film may be obtained by applying an organic resin.
The above-described display, preferably, further includes a terminal region for electrical connection, in which a contact-hole portion opened in the first planarization film and a flat surface portion surrounding the contact-hole portion are provided; wherein a metal conductive layer constituting the shield layer is connected to an underlying interconnection via the contact-hole portion; and a transparent conductive layer constituting the pixel electrode is in contact with the metal conductive layer on the flat surface portion from which the second planarization film is removed. An opening area of the contact-hole portion may be in a range of 100 &mgr;m
2
or less. The contact-hole portion may be configured as a plurality of contact-hole portions which are formed in the terminal region in such a manner as to be separated from each other by means of the flat surface portion. The second planarization film may be removed from the flat surface portion, and at least part of the second planarization film may remain in the contact-hole portion. The display, preferably, further includes a counter substrate on which a counter electrode is formed; wherein the counter substrate is joined to the substrate on which the pixel electrode has been formed with a specific gap put therebetween; and a liquid crystal is held in the gap.
According to the present invention, since the conductive shield layer is formed on the first planarization film covering the thin film transistor, the step coverage of the shield layer is enhanced and the uniformity of the thickness of the shield layer is improved. As a result, the shield layer exhibits a sufficient shielding performance, to thereby significantly reduce leakage light. This makes it possible to suppress occurrence of light leakage current even under light irradiation of a high brightness. Also, according to the present invention, steps of the shield layer are buried by covering the surface of the shield layer with the second planarization film. The pixel electrode is formed on the planarized surface of the second planarization film, and an alignment layer is formed to cover the pixel electrode and is subjected to a liquid crystal alignment treatment. Since the surface of alignment layer being in contact with the liquid crystal is smoothened, it can be uniformly subjected to the alignment treatment. In this way, by adopting the structure in which the conductive shield layer is put between the upper and lower planarization films each of which is made from an insulating material, it is possible to improve the shielding performance and the alignment characteristic of a transmission type liquid crystal display.
REFERENCES:
patent: 6057896 (2000-05-01), Rho et al.
patent: 6057897 (2000-05-01), Ichikawa et al.
patent: 6075580 (2000-06-01), Kouchi
patent: 6078366 (2000-06-01), Dohjo et al.
patent: 6246070 (2001-06-01), Yamazaki et al.
patent: 6261971 (2001-07-01), Maekawa et al.
patent: 6278131 (2001-08-01), Yamazaki et al.
patent: 6329672 (2001-12-01), Lyu et al.
patent: 6348368 (2002-02-01), Yamazaki et al.
patent: 6482684 (2002-11-01), Yamazaki
patent: 6555420 (2003-04-01), Yamazaki
patent: 2002/0132399 (2002-09-01), Shibata et al.
patent: 2002/0179908 (2002-12-01), Arao
Wolf, Ph.D., Stanley, “Multilevel-Interconnect Technology for VLSI and ULSI,” Silicon Processing for the VLSI Era—vol. 2: Process Integration, Lattce Press, 1990, pp. 229-236 and 238-239.
Fukumoto Hirohide
Hashimoto Makoto
Kadota Hisashi
Sato Takusei
Kananen Ronald P.
Rader & Fishman & Grauer, PLLC
Thomas Toniae M.
Zarabian Amir
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