Display

Details Display Display

2001-09-04

2004-10-19

Wu, Xiao (Department: 2674)

Computer graphics processing and selective visual display system

Plural physical display element control system

Display elements arranged in matrix

C345S055000, C345S090000, C345S098000, C345S100000, C345S559000, C345S560000, C349S041000, C348S790000, C348S792000

Reexamination Certificate

active

06806854

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an active matrix display. In this context, the term “display” includes not only devices intended to be viewed directly by a viewer but also devices for generating or modulating light for other purposes, for example optical processing. Thus, active or light-generating and passive or light-varying spatial light modulators are encompassed by the term “display” herein.
2. Description of the Related Art
FIG. 1
of the accompanying drawings illustrates a typical known type of active matrix display comprising an active matrix
1
of N rows and M columns of picture elements (pixels). The display comprises a data line driver
2
for receiving data at an input
3
and for supplying analogue data voltages to electrodes, such as
4
, of liquid crystal pixels via data lines, such as
5
. Each pixel comprises a TFT
6
which is connected between the pixel electrode
4
and the respective data line
5
so that columns of pixels are connected to common data lines. The gates of the transistors
6
are connected to scan lines
7
in rows with each scan line being connected to a scan line driver
8
which enables each row of pixels in turn for refreshing of a display row or line.
The data line driver
2
may receive analogue video data or digital video data. In the case of digital video data, the data line driver performs digital/analogue conversion so as to convert the incoming pixel display data to a voltage suitable for application to the pixels in order to display the desired image. The digital/analogue conversion may be non-linear so as to compensate for the generally non-linear liquid crystal voltage/light transmission characteristics.
There are several difficulties to overcome in order to integrate the circuitry such as the data line driver
2
monolithically on the same substrate as the active matrix. These difficulties generally increase with increasing required frequency of operation of the data line driver
2
and arise from: the relatively low semiconductor performance of poly-silicon transistors; and integration density Which is limited by the lithographic resolution achievable over a large substrate area. These factors set limits on the complexity of the data line driver before operating frequency, circuit area and power consumption become problematic
Digital display data are typically supplied to the digital data driver in serial form. The data are segmented into groups, generally referred to as lines of data, with each line of data corresponding to one of the N rows of pixels in the active matrix
1
. Starting with the top row of pixels in the matrix
1
, the data are input line by line, progressing down the display.
Within each line of data, there are M items of data, each item of which is a digital representation of a pixel display state. Usually, within each line of data, the item of data corresponding to the left-most pixel in a row is input first and is followed by items of data corresponding to pixels progressing from left to right along the row.
The data are supplied to all of the pixels of the active matrix at a frequency known as the frame rate F. In order to achieve this, the data rate f must be greater than or equal to F.N.M. The (horizontal) line time, which is the period between consecutive horizontal synchronisation (HSYNC) pulses, must be less than or equal to 1/FN.
The waveforms illustrated in
FIG. 2
of the accompanying drawings illustrate an example of the way in which digital signals are supplied to the digital data driver
2
. The signal HSYNC is activated between each line of data and signifies the start of transmission of a line of data. Within each line of data, items D
1
, D
2
, . . . DM are transmitted serially.
Known types of monolithically integrated digital data drivers may be categorised into two main types depending on the time interval between when the digital data are transmitted and the corresponding analogue data are written to the data lines. The discrimination point is indicated by time tx in FIG.
2
. If a line of data is written to the corresponding row of pixels before the time tx, the driving method is referred to as “point-at-a-time”. If a line of data is written to the corresponding row of pixels after the time tx, the driving method is referred to as “line-at-a-time”.
In line-at-a-time driving, in any one line time, the digital data driver may be sampling digital data for the current line while simultaneously converting the previous line of data from digital to analogue format and supplying the analogue data to the data lines. An advantage of this technique is that a whole line time is available (from when the last item DM of data is supplied until the next but one signal HSYNC) for digital/analogue conversion, writing analogue data to the data lines, and scanning the data from the data lines onto the electrodes of the row of pixels. This relatively large time period reduces the performance requirements of driver circuitry and particularly digital/analogue converter (DAC) circuitry, thus allowing implementation with lower performance processes. However, a disadvantage of this technique is that at least one entire line, and generally two entire lines, of digital data storage registers are required. Further, many DAC circuits are required. This in turn requires a relatively large physical area in the integrated circuit, particularly when the feature size of transistors is not very small as in the case of many poly-silicon TFT processes.
FIG. 3
of the accompanying drawings illustrates in block schematic form a known monolithically integrated digital data driver which is integrated on the same substrate as an active matrix using essentially the same processing steps. The driver comprises M input registers
10
which receive “single phase” digital data in parallel at a frequency of f and a clock at the frequency f. The input registers are connected to M storage registers
11
, which thus receive “M phase” digital data at a frequency of f/M. The registers
11
supply the M phase digital data at the same frequency to M digital to analogue converters
12
, which supply M phase analogue data at the same frequency to the active matrix
1
.
The digital data are supplied at the frequency f in such a way that a complete line of data is sampled and stored in the input registers
10
. Following storing of a complete line, all the digital data are transferred to the storage registers
11
, which allows the input registers to sample and store the next line of data during the next line time while the data in the registers
11
are being converted by the converters
12
to analogue data, which are supplied to the data lines of the matrix
1
. An arrangement of this type is disclosed in Y. Matsueda, T. Ozawa, M. Ximura, T. Itoh, K. Nakazawa, and H. Ohsima, “A 6-bit colour VGA low-temperature poly-Si TFT-LCD with integrated digital data drivers”. Society for information Display 98 Digest, pages 879-882, 1998, which also indicates the large amount of substrate area required for such an arrangement. In fact it has not been possible to implement such an arrangement on only one side of the active matrix substrate. Instead, “tops” and “bottom” digital drivers are connected to intedigitated sets of data lines. A further problem with this arrangement is the difficulty in matching the performance of the converters
12
.
FIG. 4
of the accompanying drawings illustrates a known modified type of digital data driver which is also integrated on the same substrate as the active matrix using essentially the same processing steps and which attempts to reduce the required area and minimise the number of transistors by multiplexing and demultiplexing around the DACs
12
. The outputs of the storage registers
11
are connected to an M to m phase multiplexer
13
, which selects m of the register outputs at a time and supplies these to m DACs
12
, where m is less than M. This operation is repeated M/m times per line time so that all M “units” of data are converted to analogue form during

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