Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor
Reexamination Certificate
2001-03-26
2004-03-16
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
C438S108000, C438S112000, C438S121000, C438S124000, C438S125000, C438S127000, C438S025000, C438S026000, C438S051000, C438S055000, C438S064000, C257S678000, C257S687000
Reexamination Certificate
active
06706553
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to processes for the fabrication of a microelectronic package. In particular, the present invention relates to a dispensing process that encapsulates at least one microelectronic die within a microelectronic package core to form a microelectronic package.
2. State of the Art
Higher performance, lower cost, increased miniaturization of integrated circuit components, and greater packaging density of integrated circuits are ongoing goals of the computer industry. As these goals are achieved, microelectronic dice become smaller. Of course, the goal of greater packaging density requires that the entire microelectronic die package be equal to or only slightly larger (about 10% to 30%) than the size of the microelectronic die itself. Such microelectronic die packaging is called a “chip scale packaging” or “CSP”.
As shown in
FIG. 22
, true CSP involves fabricating build-up layers directly on an active surface
204
of a microelectronic die
202
. The build-up layers may include a dielectric layer
206
disposed on the microelectronic die active surface
204
. Conductive traces
208
may be formed on the dielectric layer
206
, wherein a portion of each conductive trace
208
contacts at least one contact
212
on the active surface
204
. External contacts, such as solder balls or conductive pins for contact with an external component (not shown), may be fabricated to electrically contact at least one conductive trace
208
.
FIG. 22
illustrates the external contacts as solder balls
214
, which are surrounded by a solder mask material
216
on the dielectric layer
206
. However, in such true CSP, the surface area provided by the microelectronic die active surface
204
generally does not provide enough surface for all of the external contacts needed to contact the external component (not shown) for certain types of microelectronic dice (e.g., logic).
Additional surface area can be provided through the use of an interposer, such as a substrate (substantially rigid material) or a flex component (substantially flexible material).
FIG. 23
illustrates a substrate interposer
222
having a microelectronic die
224
attached to and in electrical contact with a first surface
226
of the substrate interposer
222
through small solder balls
228
. The small solder balls
228
extend between contacts
232
on the microelectronic die
224
and conductive traces
234
on the substrate interposer first surface
226
. The conductive traces
234
are in discrete electrical contact with bond pads
236
on a second surface
238
of the substrate interposer
222
through vias
242
that extend through the substrate interposer
222
. External contacts
244
(shown as solder balls) are formed on the bond pads
236
. The external contacts
244
are utilized to achieve electrical communication between the microelectronic die
224
and an external electrical system (not shown).
The use of the substrate interposer
222
requires a number of processing steps. These processing steps increase the cost of the package. Additionally, even the use of the small solder balls
228
presents crowding problems which can result in shorting between the small solder balls
228
and can present difficulties in inserting underfill material between the microelectronic die
224
and the substrate interposer
222
to prevent contamination and provide mechanical stability. Furthermore, current packages may not meet power delivery requirements for future microelectronic dice
224
due to thickness of the substrate interposer
222
, which causes land-side capacitors to have too high an inductance.
FIG. 24
illustrates a flex component interposer
252
wherein an active surface
254
of a microelectronic die
256
is attached to a first surface
258
of the flex component interposer
252
with a layer of adhesive
262
. The microelectronic die
256
is encapsulated in an encapsulation material
264
. Openings are formed in the flex component interposer
252
by laser ablation through the flex component interposer
252
to contacts
266
on the microelectronic die active surface
254
and to selected metal pads
268
residing within the flex component interposer
252
. A conductive material layer is formed over a second surface
272
of the flex component interposer
252
and in the openings. The conductive material layer is patterned with standard photomask/etch processes to form conductive vias
274
and conductive traces
276
. External contacts are formed on the conductive traces
276
(shown as solder balls
248
surrounded by a solder mask material
282
proximate the conductive traces
276
).
The use of a flex component interposer
252
requires gluing material layers which form the flex component interposer
252
and requires gluing the flex component interposer
252
to the microelectronic die
256
. These gluing processes are relatively difficult and increase the cost of the package. Furthermore, the resulting packages have been found to have poor reliability.
Therefore, it would be advantageous to develop new apparatus and techniques to provide additional surface area to form traces for use in CSP applications, which overcomes the above-discussed problems.
REFERENCES:
patent: 5048179 (1991-09-01), Shindo et al.
patent: 5457299 (1995-10-01), Blais et al.
patent: 5497033 (1996-03-01), Fillion et al.
patent: 6025995 (2000-02-01), Marcinkiewicz
patent: 6154366 (2000-11-01), Ma et al.
patent: 6232667 (2001-05-01), Hultmark et al.
patent: 6239482 (2001-05-01), Fillion et al.
patent: 6271469 (2001-08-01), Ma et al.
patent: 6320127 (2001-11-01), Nagarajan et al.
patent: 6423570 (2002-07-01), Ma et al.
patent: 2002/0070443 (2002-06-01), Mu et al.
patent: 2002/0074641 (2002-06-01), Towle et al.
patent: 0604005 (1994-06-01), None
patent: 62004351 (1987-01-01), None
patent: 3155144 (1991-07-01), None
patent: 10092970 (1998-04-01), None
patent: WO-99/56316 (1999-11-01), None
U.S. patent application Ser. No. 09/438,221, filed Nov. 12, 1999.
U.S. patent application Ser. No. 09/679,733, filed Oct. 4, 2000.
U.S. patent application Ser. No. 09/658,819, filed Sep. 8, 2000.
U.S. patent application Ser. No. 09/660,755, filed Sep. 13, 2000.
U.S. patent application Ser. No. 09/660,757, filed Sep. 13, 2000.
U.S. patent application Ser. No. 09/733,289, filed Dec. 8, 2000.
U.S. patent application Ser. No. 09/738,117, filed Dec. 15, 2000.
U.S. patent application Ser. No. 09/692,908, filed Oct. 19, 2000.
U.S. patent applicatiion Ser. No. 09/691,738, filed Oct. 18, 2000.
U.S. patent application Ser. No. 09/640,961, filed Aug. 16, 2000.
U.S. patent application Ser. No. 09/884,595, filed Jun. 18, 2001.
Cuendet John
Johnson Kyle
Towle Steven
Intel Corporation
Lee Jr. Granvill D
Schwegman Lundberg Woessner & Kluth P.A.
Smith Matthew
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