Disparity and transition density control system and method

Details Disparity and transition density control system and method Disparity and transition density control system and method

2000-10-19

2001-10-16

Williams, Howard L. (Department: 2635)

Coded data generation or conversion

Digital code to digital code converters

To or from minimum d.c. level codes

C341S050000, C708S400000, C708S410000

Reexamination Certificate

active

06304196

ABSTRACT:

CROSS-REFERENCE TO THE ATTACHED APPENDIX
Appendix A (which is part of the present disclosure as a paper appendix and will be converted to a microfiche appendix prior to the issuance of a patent) is attached herewith and incorporated herein by reference in its entirety. Appendix A contains listings of computer programs and related data including the software source code for implementing an embodiment of the invention as described more completely below.
A portion of the disclosure of this patent document contains material that is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the Patent and Trademark Office patent files or records, but otherwise reserves all copyright rights whatsoever.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to communication systems and, more particularly, to systems and methods for signal encoding and decoding.
2. Related Art
A typical communication system employs signal encoding and decoding to achieve many significant advantages such as efficient data transmission, error correction, combating channel interference, or ensuring communication secrecy. One example of an encoder is an 8 bit to 10 bit encoder (also referred to as an 8B/10B encoder) that encodes the incoming data with certain characteristics such as run length, transition density, and direct current (DC) balance. Run length refers to the number of identical contiguous symbols permitted at the encoder output. Transition density refers to the number of symbol changes (i.e., transitions from one symbol to the other symbol) for a given number of symbols, with a minimum number generally necessary for receiver synchronization. DC balance refers to providing an approximately equal number of binary ones and zeros, which for example, correspond to respective positive and negative values to allow for alternating current (AC) coupling. The characteristics above are related as, for example, a large number of contiguous binary ones would produce a large positive DC signal and run length, but no transitions.
It is generally desirable to have codes that are efficient (i.e., a large ratio of information digits per word to word length). Conventional encoders, such as the 8B/10B encoder, do generally eliminate disparity, which is the difference between the number of binary ones and zeros in a given block of data, or the DC component of the signal and also provide sufficient transition density. One drawback, however, is that these encoders are not very efficient. For example, the 8B/10B encoder operates at the byte level by taking 8 bits to provide an encoded output of 10 bits. Consequently, the 8B/10B encoder adds two additional bits for every eight bits resulting in an overhead of twenty percent. This inefficiency or additional overhead results in associated delays and costs such as increased transmission times, storage space, and overall channel capacity and bandwidth.
As a result, there is a need for a more efficient signal encoder and decoder while still providing desirable characteristics such as low disparity and sufficient transition density.
SUMMARY OF THE INVENTION
In accordance with some embodiments of the present invention, an efficient signal encoder and decoder is provided that requires less overhead than conventional signal encoders and decoders. The signal encoder/decoder of the present invention minimizes disparity or DC value of a data frame (i.e., block of data) and ensures sufficient transition density by employing Walsh-Hadamard transform techniques. The size of the data frame is scalable such as, for example, frame sizes corresponding to powers of 2 (e.g., 2, 4, 8, and 16) or three times a power of two.
In accordance with an embodiment of the present invention, a data encoding apparatus comprises at least one disparity counter that calculates the disparity for a group of data bits and a Hadamard Transform that generates possible disparity values from the calculated disparity provided by the disparity counter. A minimum disparity value for the group of data bits can then be determined.
In accordance with another embodiment of the present invention, a method of encoding data comprises receiving a group of data bits, calculating the disparity for the group of data bits, and generating possible disparity values from the disparity calculation by employing a Walsh-Hadamard Transform to determine a minimum disparity value for the group of data bits.
A more complete understanding of the systems and methods for signal encoding and decoding will be afforded to those skilled in the art, as well as a realization of additional advantages thereof, by a consideration of the following detailed description of one or more embodiments. Reference will be made to the appended sheets of drawings that will first be described briefly.


REFERENCES:
patent: 4238984 (1980-12-01), Watanabe
patent: 4446530 (1984-05-01), Tsuboka
patent: 5311176 (1994-05-01), Gurney
patent: 5726925 (1998-03-01), Hyun et al.
Richard F. Lyon, “Two-Level Block Encoding for Digital Transmission”,IEEE Transaction On Communications, pp. 1438-1441 (Dec. 1973).
A.X. Widmer and P.A. Franaszek, “A DC-Balanced, Partitioned-Block, 8B/10B Transmission Code”,IBM J. Res. Develop,pp. 440-451 (Sep. 1983).

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