Active solid-state devices (e.g. – transistors – solid-state diode – With means to control surface effects – Insulating coating
Reexamination Certificate
1999-02-25
2002-04-30
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
With means to control surface effects
Insulating coating
C257S637000, C438S448000, C438S761000, C438S950000
Reexamination Certificate
active
06380610
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to processes for the manufacture of semiconductor devices and more particularly to processes for forming field isolation.
2. Description of Prior Art
The formation of integrated circuit devices on silicon substrates requires that a means be provided to electrically isolate the various circuit components from each other. In many cases p
junctions themselves can be used to form at least part of the necessary isolation. Most isolation requirements, which cannot be resolved by circuit design, relate to the lateral isolation of devices. To some extent, junction isolation can be used here also. However, as device technology leads to smaller and smaller geometries as well as shallower structures, junction isolation technology becomes very limited.
The successful use of silicon for integrated circuits for the last thirty years can, in part, be attributed to the marvelous insulating properties of it's oxide. No other commonly known semiconductor material has this unique feature. Thus silicon oxide has become well established as the isolation material for integrated circuit chips. Earliest usage of this material involved growing it on the substrate in selected regions which are defined by an oxidation masking material. To this end, silicon nitride came into widespread use. Referring to
FIG. 1
, a pad silicon oxide film
22
several hundred Angstroms thick is grown on the surface of a silicon wafer
20
. Next a film of silicon nitride
24
is deposited to a thickness of several thousand Angstroms using a chemical-vapor-deposition process. The pad oxide
22
is used as a buffer layer, preventing the highly stressed silicon nitride from causing dislocations in the silicon.
Using standard photolithographic techniques followed by etching, a pattern is defined in the oxide
itride mask, leaving bare those regions
26
on the silicon which are to become isolation regions. Referring next to
FIG. 2
, the wafer
20
is subjected to an oxidizing ambient at elevated temperatures, during which the exposed areas are converted to silicon oxide
28
. The oxidation proceeds at the oxide-silicon interface. Thereby pockets of silicon oxide
27
several thousand Angstroms deep can be formed in the patterned areas. These pockets
27
provide the necessary electrical isolation for the subsequently formed semiconductor devices. The process just described has become known by several names, one of which is LOCOS an acronym for LOCal Oxidation of silicon. LOCOS has been practiced for over twenty-five years and has been adapted to many specific applications. One of the problems with conventional LOCOS, illustrated in
FIG. 2
is that the pad oxide
22
permits oxidation to take place under the silicon nitride mask, pushing up the edge of the mask and thereby leaving a raised portion of the oxide around the mask perimeter, known as “Birds Head”
28
and a protrusion of oxide under the edge of the oxidation mask
29
, caused by diffusion of oxidant through the thin pad oxide
22
, known as “Birds Beak”. The birds head
28
, being a protrusion above the surface, causes shadowing and thinning problems with subsequently deposited metallization stripes traversing across it. Thin areas in metal interconnection lines constitute “weak spots” and are subject to increased current density, heating, and subsequent electrical failure. The birds beak
29
can be reduced by using as thin as possible pad oxide
22
or by stiffening the mask by using a thicker silicon nitride layer
24
. In some instances, a sidewall oxidation barrier is formed along the mask edge to prevent penetration of the oxidant under the nitride mask. Unfortunately, these practices lead to an abrupt feature
25
wherein the high shearing stresses are produced in the silicon which lead to the formation of dislocations. These dislocations propagate diagonally into the device active regions causing junction failure.
Typically, the field oxide is grown at temperatures above 1,000° C. At these temperatures, stresses which would be developed due to the volume expansion, are relieved by plastic flow of the oxide. However, upon completion of the oxidation, and when the wafer is cooled, sufficient plastic flow is no longer able to relieve stresses below about 960° C. (Wolf, S.,“Silicon Processing for the VLSI Era”, Vol.2, Lattice Press, Sunset Beach, Calif., (1990),p693). Thermal stresses now develop due to the difference in thermal expansion coefficients of the silicon oxide and the silicon. The profile of the field oxide is now the determining factor for the distribution of stresses within the silicon. Abrupt features in the silicon/silicon oxide profile, such as
25
in
FIG. 2
, are responsible for high values of x-y shearing stresses which produce dislocations. Such abrupt features
25
occur when a stiff mask edge is used to control the field oxidation.
The compressive stresses developed within the growing field oxide also have been observed to retard the oxidation rate of silicon. Known as the field oxide thinning effect, this phenomena is observed when field oxide is grown in mask openings below about 0.5 to 0.6 microns. See for example, P. Belluti and M. Zen in J. Electrochem. Soc. 143, (1996) p 2953.
Efforts to diffuse the abruptness of a stiff mask edge and to control the extent of birds beak encroachment into the silicon active area as well as the shape of the birds head, have been made using “L” shaped spacers which form a foot at the mask edge. Jang U.S. Pat. No. 5,397,733 describes several ways in which these spacers can be formed. An example of such a spacer is shown in FIG.
3
. The thin nitride foot
30
surrounding the periphery of the thicker nitride mask provides a region of more flexible mask at the edge of the opening, thereby allowing easier expansion of the growing field oxide under it. The thicker, and therefore stiffer, section
32
continues to constrict the birds beak. By proper selection of the thickness and length of the mask foot
30
as well as the thickness of the more rigid portion
32
, it becomes possible to tailor the mask edge to provide a field oxide profile
36
with reduced stress at the expense of minimal birds beak encroachment. Jang cites prior art difficulties in forming the L-shaped spacer, specifically, difficulties in controlling thickness and length of the spacer. Indeed, the control of these parameters in a manufacturing environment is difficult.
The precise tailoring of the field oxidation mask edge becomes even more critical as device geometries shrink into the sub-half micron range. As field oxide widths approach these dimensions oxidation rates are significantly reduced and stress induced crystalline defects cause serious degradation of the semiconductor devices. The balance between reducing birds beak encroachment and preventing stress induced dislocations requires an even greater control of the field oxide oxidation mask edge. The invention herein described provides an added dimension in mask engineering. In addition, the invention eliminates the process steps required by Jang et.al. for spacer formation.
Yook et.al. U.S. Pat. No. 6,445,990 teaches the use of a mask comprising two silicon nitride layers separated by a silicon oxide layer. Each silicon nitride layer is patterned with an opening after it is formed, thereby necessitating two photolithographic steps. The opening in the second nitride layer is smaller than that in the first nitride layer and is concentric with it. After the field oxide is grown a third photolithographic step protects the field isolation region while the oxidation mask and the birds beak region are removed. This method effectively uses the stiff mask approach to reduce birds beak and makes no effort to subdue abrupt oxide contours or reduce stress formation.
Rao U.S. Pat. No. 5,294,563 similarly uses an edge sealed poly buffered nitride mask wherein nitride sidewalls on the polybuffered mask edge provide an edge seal to all but the thinner than conventional pad oxide. The result is similar to other
Hock David Yeo Yong
Loiko Konstantin V.
Peidous Igor V.
Quek Elgin
Chartered Semiconductor Manufacturing Ltd.
Chaudhuri Olik
Duy Mai Anh
Pike Rosemary L. S.
Saile George O.
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