Disk unit with processors which detect cache status and control

Details Disk unit with processors which detect cache status and control Disk unit with processors which detect cache status and control

1989-10-10

1993-08-31

Harrell, Robert B.

Boots, shoes, and leggings

3642481, 364260, 3642384, 3642434, 364DIG1, G06F 1312

Patent

active

052416402

ABSTRACT:
A disk unit control apparatus (DKC) comprises a cache memory provided between a CPU and an external memory (DKU) storing the information exchanged with the CPU, the cache memory holding temporarily copies of the information stored in the DKU. A request from the CPU for access to the information stored in the DKU is met as far as possible by use of the information held in the cache memory. First transfer routes of information between the CPU and the cache memory is greater in number than second transfer routes of information between the cache memory and the DKU. This makes it possible that even when direct accesses to the DKU in the same number as the second transfer routes occur in each of the first transfer route, acesses to the cache memory which may arise from other CPUs are capable of being effected through the remaining ones of the first transfer routes. As a result, a cache memory accessible with high speed is obtained, and the utilization efficiency of the data stored in the cache memory is substantially improved, improving the data throughput between the CPU and the DKU.

REFERENCES:
patent: 4603380 (1986-07-01), Easton
patent: 4916605 (1990-04-01), Beardsley
patent: 4920478 (1990-04-01), Furhya
patent: 4930066 (1990-05-01), Yokota
patent: 4951246 (1990-08-01), Fromm
patent: 4972364 (1990-11-01), Baurett
patent: 4974156 (1990-11-01), Harding
patent: 5060145 (1991-10-01), Scheuneman
patent: 5072420 (1991-12-01), Conley

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