Dynamic magnetic information storage or retrieval – General processing of a digital signal – Data clocking
Reexamination Certificate
1999-05-25
2002-01-08
Neal, Regina Y. (Department: 2651)
Dynamic magnetic information storage or retrieval
General processing of a digital signal
Data clocking
C360S068000, C360S046000
Reexamination Certificate
active
06337778
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to generating a write clock signal for writing data in hard disk drives. More particularly, the present invention relates to a disk drive employing vector addition of primary phase write clock signals for generating a secondary phase write clock signal.
2. Description of the Prior Art
A huge market exists for hard disk drives for mass-market host computer systems such as servers, desktop computers, and laptop computers. To be competitive in this market, a hard disk drive must be relatively inexpensive, and must accordingly embody a design that is adapted for low-cost mass production. In addition, it must provide substantial capacity, rapid access to data, and reliable performance. Numerous manufacturers compete in this huge market and collectively conduct substantial research and development, at great annual cost, to design and develop innovative hard disk drives to meet increasingly demanding customer requirements.
Each of numerous contemporary mass-market hard disk drive models provides relatively large capacity. Nevertheless, there exists substantial competitive pressure to develop mass-market hard disk drives having even higher capacities. Another requirement to be competitive in this market is that the hard disk drive must conform to a selected standard exterior size and shape often referred to as a “form factor.” Generally, capacity is desirably increased without increasing the form factor or the form factor is reduced without decreasing capacity.
Satisfying these competing constraints of low-cost, small size, and high capacity requires a design that provides high format efficiency and high areal storage density. Format efficiency relates to the percentage of available area that is available for storing user data rather than being consumed by control data, gaps, etc. Areal storage density relates to the amount of data storage capacity per unit of area on the recording surfaces of the disks. The available areal density may be determined from the product of the track density measured radially and the linear bit density measured along the tracks. The available linear bit density depends on numerous factors including the performance capability of certain circuitry that is commonly referred to as a “write channel” and a “read channel.” The write channel includes write precompensation circuitry that provides a write clock signal having a channel frequency corresponding to the rate at which data is to be written on the disk surface (the “data rate”). Increasing the data rate can increase the linear bit density. As the linear bit density increases, nonlinear magnetic transition shifts (non-linear intersymbol interference) may occur due to the magnetic interactions between closely spaced magnetic transitions. However, the read channel includes sampled data detection circuitry (such as a PRML channel, a EPR4 channel, and a E
2
PR4 channel) that assumes linear intersymbol interference between magnetic transitions recorded on the disk surface during the write operation. Therefore, the write precompensation circuitry in the write channel shifts the phase of the write clock signal in order to shift the time that magnetic transitions are recorded on the disk surface in order to compensate for this nonlinear transition shift problem. The phase shift magnitude in the write clock signal depends on the data pattern that has been and will be recorded on the recording surface.
It is known to provide a write precompensation circuit that includes several time delay circuits for generating write clock signals having a phase shift that is selected based on the data pattern. The phase shift generated by each time delay circuit is a percentage of the write clock signal. The resolution of the phase shift is determined by the number of delay circuits in the write precompensation circuit (e.g., 5% resolution requires 20 delay circuits). Each delay circuit requires sufficient current for generating the appropriate phase shifts within the clock period.
As the data rate and linear bit density increase, finer resolutions of the clock period are desirable. Increasing the number of time delay circuits can provide finer resolution (e.g., 2% resolution requires 50 delay circuits). However, this can increase the cost of the write precompensation circuit. Also, the additional time delay circuits can result in increased power consumption. Furthermore, increased current is required for each of the time delay circuits in order to timely generate the appropriate phase shifts within the increased clock period. This increased current can also result in increased power consumption.
For example, U.S. Pat. No. 5,598,364 (the '364 patent) discloses a write precompensation circuit that includes current controlled delay buffers connected to form a delay line having selectable output taps for providing time shift delays. The delay of each delay buffer is controllable by a secondary control current derived from a master control current such that the delay is a percentage of an oscillator period. The master control current is also used to control the period of a master write clock generated by a current-controlled ring oscillator of delay buffers. A disadvantage with the write precompensation circuit disclosed in the '364 patent is that the magnitude of the resolution for the time delay is limited by the number of delays buffers in the write precompensation circuit.
U.S. Pat. No. 5,541,961 (the '961 patent) discloses a digital communication system including a phase synthesizer for use in clock extraction circuitry. The phase synthesizer disclosed in the '961 patent requires complex circuitry for weighting and integrating two square wave signals to generate a phase-shifted output signal that is used in the clock extraction circuitry.
There is a need for a write precompensation circuit in a hard disk drive which produces finer resolution incremental steps for producing phase shifts in the write clock signal without requiring excessive power or excessive amounts of added circuitry.
SUMMARY OF THE INVENTION
The invention can be regarded as a disk drive comprising a disk having a recording surface and write means for writing a sequence of symbols in a continuous-time signal on the recording surface. The disk drive includes a frequency generator for generating a plurality of primary phase write clock signals having a channel frequency f
ch
, each of the primary phase write lock signals having a selected primary phase shift from another one of the primary phase write clock signals. The disk drive further includes a programmable phase synthesizer for generating a secondary phase write clock signal having the channel frequency f
ch
and a selected secondary phase shift from one of the primary phase write clock signals. The programmable phase synthesizer includes programmable means for selecting two of the primary phase write clock signals and means for performing vector addition of the selected primary phase write clock signals to generate the secondary phase write clock signal. The disk drive includes means responsive to the secondary phase write clock signal for providing at least one of the symbols in the sequence of symbols to the write means.
The invention can also be regarded as a disk drive comprising a disk having a recording surface and a write means for writing a sequence of symbols in a continuous-time signal on the recording surface. The disk drive includes a frequency generator for generating a plurality of primary phase write clock signals having a channel frequency f
ch
, each of the primary phase write clock signals having a selected primary phase shift from another one of the primary phase write clock signals. The disk drive further includes a plurality of programmable phase synthesizers for generating a plurality of secondary phase write clock signals having the channel frequency f
ch
and a selected secondary phase shift from one of the primary phase write clock signals. Each programmable phase synthes
Neal Regina Y.
Shara Milad G
Western Digital Technologies Inc.
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