Disk drive controller with a posted write cache memory

Details Disk drive controller with a posted write cache memory Disk drive controller with a posted write cache memory

1995-03-13

1996-12-17

Beausoliel, Jr., Robert W.

39518207, G06F 1100

Patent

active

055862489

ABSTRACT:
A disk array controller includes a local microprocessor, a bus master interface, a compatible interface, buffer memory and a disk interface. The controller includes a DMA controller between the microprocessor, the bus master interface, the compatibility interface and the buffer memory. DMA controllers are also provided between the disk interface and the buffer memory. One of these DMA channels includes an XOR engine used to develop parity information used with the disk array. The various DMA controllers are cycled to allow access to the buffer memory and the disk interface. A posted write memory system is connected as a selectable disk drive to the disk interface. The posted write memory system includes mirrored, parity checked and battery backed semiconductor memory to allow posted write data to be retained during power down conditions with only a very small change of data loss.

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