Dynamic magnetic information storage or retrieval – General processing of a digital signal – Head amplifier circuit
Reexamination Certificate
2002-07-23
2003-05-13
Faber, Alan T. (Department: 2651)
Dynamic magnetic information storage or retrieval
General processing of a digital signal
Head amplifier circuit
C360S053000, C360S051000, C360S077080, C360S078140
Reexamination Certificate
active
06563656
ABSTRACT:
BACKGROUND OF THE INVENTION
a) Field of the Invention
The present invention relates to a disk device, and in particular to a circuit for processing servo information and a method of generating a signal representative of the position of a head for reading/writing data in an auxiliary storage of an electronic data processing device using a disk type storage medium.
b) Description of the Related Art
As personal computers have recently been improved in performance and their costs have been reduced, data storage devices, in particular magnetic disk devices, are strongly demanded to provide a large quantity of storage capacity and to reduce its cost.
For this reason, the electronic circuits for disk devices have been year by year integrated into smaller circuits while incorporating large storage capacity with increasing technology. Prior to describing the operation of the electronic circuit, current disk formats will be described.
FIGS. 1A
,
1
B,
1
C and
1
D show an example of a disk format. A disk format is mainly classified into a sector (SSCT
78
in
FIG. 1B
) provided for controlling the position of a head on a recording medium, which records/reproduces a data, and a data sector (DSCT
79
) provided for storage of user data. The SSCT
78
comprises an Automatic gain control gap (AGCG)
60
, a Servo mask (SVMK)
61
, an Index mark (IDXM)
76
/Sector mark (SCTM)
77
, a Cylinder address (CYL)
63
, a Servo sector address (SSA)
64
and a Positioned pattern (POS)
65
.
The AGCG
60
and SVMK
61
are areas provided for controlling the read gain of servo information and for detecting the leading position of SSCT
78
, respectively. The IDXM
76
/SCTM
77
are areas for identifying the leading position of a track or sector. The CYL
63
and the SSA
64
are areas for storing the cylinder number (track number) and the servo sector address, respectively.
The POS
65
usually stores therein four pieces of information for precisely positioning a head among cylinders (burst signals A
66
, B
67
, C
68
, D
69
) and is used for controlling the precise positioning operation (settling) and tracking (following) operation to constantly position the head on a desired cylinder.
On the other hand, the DSCTA
79
comprises an Inter sector gap (ISG)
70
, PLO pattern (PLO)
71
, byte sync data (BS)
72
, user data (DATA)
73
, and an Error correcting code (EGC)
74
. The ISG
70
is an area for absorbing the variations in rotation of the disk. The PLO
71
is an area for synchronization of read data with clock. The BS
72
is an area for detecting the timing in which serial data is converted into parallel data. The DATA
73
is an area for storing the user data therein. The ECC
74
is an area for checking whether or not there is an error in the read DATA
73
and for correcting the error if any.
DSCTB
79
is the format in which SSCT
78
is inserted into DSCTA
79
, fundamentally. However, PLO
71
, BS
72
are repeatedly disposed. This means, while reading out, since read processing is interrupted once when passing SSCT
78
, therefore, it is necessary to carry out clock synchronization and byte synchronization to activate read processing again.
Now, the configuration of a prior art circuit for controlling the present format will be described with reference to
FIGS. 2
to
5
.
FIG. 2
is a block diagram showing the system configuration of a disk device
1
adopting a data surface servo format. The disk device
1
comprises a disc control device
2
, signal processing device
12
, motor driver
14
, R/W amplifier
13
, R/W head
7
and data surface recording medium
15
. The disk control device
2
comprises a data processing unit
3
, servo control unit
4
and CPU
5
. The data processing unit
3
comprises a host interface control unit
10
, buffer control unit
9
, drive interface unit (hereinafter referred to as “drive I/F control unit)
6
and ECC control unit
8
and may include a data buffer
11
in the data processing unit
3
.
FIG. 2
shows the system configuration in which the data buffer
11
is included in the data processing unit
3
.
In this configuration, the data processing unit
3
is integrated into single LSI (data processing device). Each of the motor driver
14
and the signal processing device
12
is integrated into single LSI.
Now, operation of each of the above-mentioned blocks will be described by a way of reproducing operation of data in a case where the disk format shown in
FIGS. 1A
,
1
B,
1
C and
1
D is adopted.
The CPU
5
calculates the address on the recording medium
15
where the data which is requested by a host computer is stored and informs the servo control unit
4
of it. The servo control unit
4
detects the CYL
63
and POS
65
via the signal processing device
12
and outputs to the motor driver
14
a control signal to cause R/W head
7
to settle on and to track the cylinder where the requested data exists. The servo control unit
4
also detects SSA
64
shown in FIG.
1
B and informs the drive I/F control unit
6
of the sector address of PSCT
79
where the R/W head
7
is positioned. The motor driver
24
controls the voice coil motor (VCM) based upon the control signal and also outputs a control signal for the spindle motor.
On the other hand, the drive I/F control unit
6
determines as to whether or not the data sector address informed from the servo control unit
4
matches a desired sector. If they match, the drive I/F control unit
6
generates a read instruction signal to the signal processing device
12
for initiating reading of data. The signal which is read out by the R/W head
7
and R/W amplifier
13
is synchronized with the read data with reference to PLO
71
shown in
FIG. 1C
in the signal processing device
12
and is discriminated into a clock and a Non return to Zero (NRZ) data. The DATA
73
shown in the drawing is processed so that the serial data is converted into parallel data based upon BS
72
and the converted data is transferred to the drive I/F control unit
6
.
The control unit
6
also transfers the parallel data to ECC control unit
8
simultaneously with the transfer to the buffer control unit
9
. In the ECC control unit
9
, error detection for DATA
73
is conducted based upon the read DATA
73
and ECC
74
. If an error is detected, the error can be corrected. If no error is detected, the DATA
73
is transferred to the host computer
16
from the buffer control unit
9
via the data buffer
11
and the host interface control unit
10
. A description of the recording operation of data will be omitted herein since the data to be recorded is transferred in a path which is substantially reverse to the reproducing operation.
The circuits which are strongly correlated with the present invention are the signal processing device
12
, servo control unit
4
and the drive I/F control unit
6
. Now, each of these blocks will be described.
FIG. 3
shows the configuration of the circuit of the signal processing device
12
, which comprises an Automatic gain control (AGC)
17
, filter
18
, burst signal detector
22
, pulse generator
19
, clock generator
20
, encoder/decoder (EN/DEC)
21
and a central processing unit interface (CPU I/F) circuit
93
A. The AGC
17
is adapted to automatically control the amplitude gain of a signal (RDATA)
44
which is read from the recording medium
25
via the read/write (R/W) amplifier
13
. The filter
18
eliminates the noise components in the signal. The pulse generator
19
is adapted to generate a digital signal (pulse) from the read out analog signal.
At this time, the above-mentioned SVMK
61
, IDXM
76
/SCTM
77
, CYL
63
and SSA
64
are fed to the servo control unit
4
as a read data pulse (RDP)
39
. The clock generator
20
generates a clock which is synchronized with the pulse which is generated in the pulse generator
19
and outputs it to EN/DEC
21
. The EN/DEC
21
encodes the NRZ data when data is written in synchronization with the sync clock and decodes the digital signal when the data is read. The EN/DEC
21
conducts conversion of parallel data into serial d
Horita Ryutaro
Miyazawa Shoichi
Miyazawa Yukie
Nara Takashi
Nishina Masatoshi
Faber Alan T.
Mattingly Stanger & Malur, P.C.
Miyazawa Yukie
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