Dishing inhibited shallow trench isolation

Details Dishing inhibited shallow trench isolation Dishing inhibited shallow trench isolation

1997-12-22

1999-07-27

Utech, Benjamin

Semiconductor device manufacturing: process

Chemical etching

Combined with the removal of material by nonchemical means

438689, 438691, 438633, H01L 21304

Patent

active

059289619

ABSTRACT:
A method for trench filling during integrated circuit manufacture is described in which the filled-in surface is dishing inhibited. To accomplish this an extra layer is introduced between the trench-defining mask material and the trench filler material. This transition layer is characterized by having a removal rate (under CMP) that is greater than that of both the mask material and the filler material. An important additional advantage is that end-point detection is now much easier because of the large difference in removal rates between the mask and transition layers.

REFERENCES:
patent: 5292689 (1994-03-01), Cronin et al.
patent: 5308438 (1994-05-01), Cote et al.
patent: 5356513 (1994-10-01), Burke et al.
patent: 5441094 (1995-08-01), Pasch
patent: 5516729 (1996-05-01), Dawson et al.
patent: 5540811 (1996-07-01), Morita
patent: 5629242 (1997-05-01), Nagashima et al.

Affiliated with

Also associated with

Rating

Dishing inhibited shallow trench isolation does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Dishing inhibited shallow trench isolation, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Dishing inhibited shallow trench isolation will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-878207