Discrimination phase margin monitor circuit,...

Details Discrimination phase margin monitor circuit,... Discrimination phase margin monitor circuit,...

2008-03-04

2008-03-04

Phan, Hanh (Department: 2613)

Optical communications

Receiver

Including postcompensation

C398S155000, C398S154000, C398S202000, C398S208000, C398S162000, C398S209000, C398S163000, C398S213000, C398S214000, C398S079000, C398S141000, C398S158000, C398S159000, C398S175000, C398S183000, C398S195000, C398S192000, C398S201000, C398S196000, C398S197000, C398S118000, C375S317000, C375S318000, C375S222000, C375S225000, C375S224000, C375S226000, C375S326000, C375S327000, C327S060000, C327S072000, C327S074000, C327S076000

Reexamination Certificate

active

10936544

ABSTRACT:
The discrimination phase margin monitor circuit (10) of the present invention comprises a first discrimination circuit (11and12) discriminating an input data signal using a clock signal extracted from the input data signal, a second discrimination circuit (13and14) discriminating the input data signal using a clock signal with a frequency different from that of the clock and an operation circuit (15and16) calculating the exclusive OR of the output signal of the first discrimination circuit and that of the second discrimination circuit and obtaining a phase margin monitor output signal by averaging the exclusive ORs.

REFERENCES:
patent: 4475210 (1984-10-01), Couch
patent: 4514854 (1985-04-01), Ashida
patent: 5736875 (1998-04-01), Sakamoto et al.
patent: 5920414 (1999-07-01), Miyachi et al.
patent: 7088927 (2006-08-01), Taga et al.
patent: 2003/0058507 (2003-03-01), Oomori
patent: 8-265375 (1996-10-01), None
patent: 11-68674 (1999-03-01), None

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