Discretization technique for multi-dimensional semiconductor dev

Details Discretization technique for multi-dimensional semiconductor dev Discretization technique for multi-dimensional semiconductor dev

1996-10-11

1999-04-20

Teska, Kevin J.

Boots, shoes, and leggings

364490, 364488, 364489, G06F 1900

Patent

active

058963030

ABSTRACT:
Disclosed is a method of improved grid generation for semiconductor device simulation. In particular, the invention includes a simple method for locating critical interfaces (e.g., oxide-silicon interfaces) and then utilizing the information to generate finer mesh elements near those boundaries where device behavior is most critical. The method of identifying critical interfaces includes the steps of examining the boundary data for each material region in the device, and then generating normal lines between adjacent boundaries to identify "thin" regions, which are generally associated with the critical interfaces. Once this occurs, a recursive subdivision algorithm may be utilized to generate a grid whose element dimensions are dependent upon their proximity to identified critical regions.

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