Oscillators – With frequency adjusting means – Step-frequency change
Reexamination Certificate
2002-12-20
2004-12-28
Mis, David (Department: 2817)
Oscillators
With frequency adjusting means
Step-frequency change
C331S016000, C331S03600C, C331S17700V
Reexamination Certificate
active
06836193
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to voltage controlled oscillators (VCO's). More specifically, a VCO that includes a discretely variable capacitance circuit in its oscillator is disclosed.
BACKGROUND OF THE INVENTION
Frequency synthesizers are widely used in modern communication systems, particularly wireless communication systems, to generate desired frequencies for modulation and demodulation. Many of the wireless protocols, for instance GSM or CDMA, support multiple frequency channels. Thus, the wireless devices used in systems supporting these protocols should be capable of transmitting and receiving signals at multiple frequencies, and the frequency synthesizers used in the wireless devices should be configurable to generate different frequencies.
Generally, a frequency synthesizer generates different frequencies by adjusting the oscillation frequency of its oscillator. Frequency synthesizers that require low phase noise and high quality of oscillation commonly employ LC tank oscillators with variable capacitors. Common variable capacitor designs often include a discretely variable capacitor for coarsely and quickly adjusting the capacitance to a desired range, and a continuously variable capacitor for fine tuning the capacitance.
Most of the existing implementations of the discretely variable capacitor fall into two categories: ones that switch among capacitors of the same size, and ones that use non-uniformly sized capacitors in a switching network. Uniformly sized capacitor designs have the disadvantage of requiring a large number of capacitors and hence a large number switches to provide a desired amount of variance in capacitance. The number of capacitors and switches can be reduced by using nonuniformly sized capacitors. Ideally, capacitor size would increase by a multiplier of 2, (1, 2, 4, 8, 16, etc.) to require a minimum number of capacitors and switches. However, such a different sized capacitor design tends to suffer from differential non-linearity (DNL) problems caused during the manufacturing process.
One approach that has been suggested to best deal with the issues described above is to use capacitors that increase in size, but not as aggressively as by powers of 2. Such a mixed radix or multiplier design is disclosed in U.S. Pat. No. 6,233,441 by Welland. This approach is a compromise that reduces the number of switches required by a one size capacitor design while reducing somewhat the introduced nonlinearities. However, nonlinearities are still introduced and switching is not minimized. It would be desirable if to develop a design that could further reduce the number of switches and avoid nonlinearities.
REFERENCES:
patent: 5519265 (1996-05-01), Latham, II
Conroy Cormac S.
Kim Beomsup
Berkana Wireless Inc.
Mis David
Van Pelt & Yi LLP
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