Discrete wafer array process

Details Discrete wafer array process Discrete wafer array process

1999-06-11

2001-06-19

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Bonding of plural semiconductor substrates

Thinning of semiconductor substrate

C438S455000, C438S456000

Reexamination Certificate

active

06248646

ABSTRACT:

FIELD OF INVENTION
This invention relates to production of silicon carbide (SiC) wafers. More particularly this invention discloses a method which enables an array of small SiC wafers to be concurrently produced on a larger, industry standard sized wafer. This allows the use of industry standard equipment and dramatically increases production rates.
BACKGROUND OF THE INVENTION
The increasingly pervasive presence of microprocessors in controls has created an increasing demand for sensors in all types of environments so that processes may be more closely monitored, operations may be more finely tuned, and so that efficiencies and emissions may be improved.
Commercially available silicon pressure sensors become unreliable above 200° C. Silicon on Insulator technology has enabled device operation to 300° C., and with costly integrated cooling systems this upper temperature limit has further increased. Large scale production is inhibited by the small size of applicable SiC wafers due to incompatability with conventional semiconductor fabrication facilities.
U.S. Pat. Nos. 5,349,207 and 5,441,911 issued to S. Malhi disclose a structure of SiC bonded to silicon and a method capable of using existing (large) silicon wafer production facilities. One problem with Malhi's structure is that its thermal budget is limited by the silicon substrate. The mismatch in coefficient of thermal expansion between SiC and silicon has the potential to create reliability problems. Another inherent problem with Malhi's structure is that the SiC wafers cannot be precisely and consistently positioned on the silicon substrate. Consequently they cannot be tightly packed. They lack much needed process control. Additionally Malhi's wafers must be sufficiently thick to insure they do not break prior to bonding.
OBJECTS AND STATEMENT OF INVENTION
It is an object of this invention to disclose a method of fabricating SiC wafers in an array on an amorphous substrate. The substrate need not be crystalline. It may be selected to have higher temperature resistance, higher temperature conductivity, and greater ruggedness than silicon. SiC has a higher coefficient of thermal expansion than silicon. In extreme temperature variations this is critical. High thermal conductivity also allows the substrate to act as a heat sink. It facilitates connection of pins thereto and may provide a radiation shield. It is particularly advantageous when integrated devices thereon comprise power transistors. Greater ruggedness is generally advantageous; the substrate may act as a circuit board. It is particularly advantageous in vibration. It is yet a further object of this invention to disclose a method which provides for the production of a precisely positioned array of wafers on a substrate. Tight process control facilitates tight packing and minimal waste. Additionally it is not necessary to undertake expensive epitaxial growth on small multiple surfaces. The cost of conventional SiC wafer production may be reduced by more than an order of magnitude. It is yet a further object of this invention to disclose a method of SiC fabrication which will facilitate production of optimally thin wafers—wafers which will have minimal parasitics when used in devices. Very thin SiC wafers also enable epitaxial growth on a top surface thereof. A final object of this invention is to disclose a structure which will facilitate integrating microelectromechanical devices with CMOS controls, and amplification circuits, on the same substrate.
One aspect of this invention provides for a method of preparing small wafers for compatibility with conventional large wafer fabrication equipment comprising the following steps: indenting a face of a large wafer to form an array of depressions thereon, each depression sized to matingly accept a lower portion of a small wafer; applying a bonding medium to an exterior side of the depressions on the indented face of the large wafer; matingly fitting the small wafers into the depressions so that the small wafers are positioned in an array on the large wafer; and, removing the top portion of the small wafers standing out of the depressions by chemical mechanical polishing so that the remaining portions of the small wafers then have a uniform thickness generally equal to the depth of the indentations in the large wafer.
Another aspect of this invention provides for a method as above wherein the small wafer is SiC and the large wafer is made from an amorphous substance which comprises SiC or aluminum nitride.
Various other objects, advantages and features of novelty which characterize this invention are pointed out with particularity in the claims which form part of this disclosure. For a better understanding of the invention, its operating advantages, and the specific objects attained by its users, reference should be made to the accompanying drawings and description, in which preferred embodiments of the invention are illustrated.


REFERENCES:
patent: 4661199 (1987-04-01), Looney et al.
patent: 5652436 (1997-07-01), Stoner

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