Discrete time digital phase locked loop

Details Discrete time digital phase locked loop Discrete time digital phase locked loop

1995-11-02

1996-11-19

Grimm, Siegfried H.

Oscillators

Automatic frequency stabilization using a phase or frequency...

Afc with logic elements

331 17, 331 25, 331 27, 375376, 455260, H03L 7093

Patent

active

055766641

ABSTRACT:
A communication receiver (100) employs a discrete time digital phase locked loop (142) for maintaining a generated signal (144) locked to a reference signal (136). The discrete time digital phase locked loop (142) includes a phase detector (202), an accumulator (219), an adder (227), and a controlled oscillator (232). The accumulator (219) is connected to the phase detector (202) and a reference signal (136) for calculating an accumulator output value equal to a first sum of a current sample generated by the phase detector (202), and all of the plurality of discrete phase error samples produced prior to the current sample. The adder (227) is connected to the phase detector (202) and the accumulator (219) for forming a second sum of the current sample and the accumulator output value. The controlled oscillator (232) receives the second sum, which is utilized for controlling the controlled oscillator (232).

REFERENCES:
patent: 4167711 (1979-09-01), Smoot
patent: 5373255 (1994-12-01), Bray et al.
Digital Control Systems by Kuo, B. C., pp. 278-279, Holt, Rinehart & Winston, Inc New York, 1980.

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