Discrete-time convolution cycle reduction with programmable...

Details Discrete-time convolution cycle reduction with programmable... Discrete-time convolution cycle reduction with programmable...

2002-09-27

2009-08-25

Ngo, Chuong D (Department: 2193)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C708S315000

Reexamination Certificate

active

07580965

ABSTRACT:
A programming algorithm reduces from θ (2N2) to θ (N2) the number of multiply-and-accumulate (MAC) instructions required to perform a discrete-time convolution on a programmable digital signal processor. Through the use of a single repeat instruction along with a single repeat count register, the algorithm dynamically changes the number of times the multiply-accumulate instruction is repeated depending upon the current term being convolved. The avoids performing the multiply-accumulate when one term is zero. The nature of the discrete-time convolution calculation and the flexibility of a re-programmable single repeat count register offers permits this. Additional instructions are required for data pointer alignment. The trade-off between reduced multiply-accumulate operations and the overhead required to achieve it is examined.

REFERENCES:
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patent: 5822609 (1998-10-01), Richter
patent: 6477555 (2002-11-01), Hartung
patent: 6643412 (2003-11-01), Hong et al.
Oppenheim et al., “Signals and Systems”, 1983. pp. 79-84.
Stanford Exploration Project, “Convolution Equation and Program”, 2 pages, Oct. 21, 1998. (http://sepwww.stanford.edu/prof/pvi/cs/paper—html
ode6.html).

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