Discrete silicon capacitor

Details Discrete silicon capacitor Discrete silicon capacitor

1999-05-26

2001-06-26

Dinkins, Anthony (Department: 2831)

Electricity: electrical systems and devices

Electrostatic capacitors

Fixed capacitor

C361S306100, C257S690000

Reexamination Certificate

active

06252760

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to capacitors. More particularly, the present invention relates to capacitors formed from two metal layers on a substrate.
2. The Background Art
Due to strong market demand for higher integrated circuit data throughputs, there is a constant push to increase signal frequencies used within modern integrated circuits.
In order to ensure that a signal being transmitted over a given conductive path within an integrated circuit are not affected by signals inductively coupled from other conductive paths, capacitors are often added in signal paths so that the amplitudes of those coupled signals are reduced, due to the reactance of the capacitor. The value of the capacitor is chosen so that desirable signals at particular frequencies pass through the capacitor with significantly less reduction in amplitude as compared to the amplitude reduction which occurs to undesirable signals at other frequencies.
FIGS. 1A and 1B
are a side view and top view respectively of an integrated circuit substrate mounted on a package, with the resulting combination being mounted on a printed circuit board.
Referring to
FIGS. 1A and 1B
, integrated circuit
10
is shown including a multilayer package
12
, a substrate
14
, and a capacitor
16
. Solder bumps
18
connect substrate
14
to package
12
. Solder bumps
20
connect package
12
to multilayer circuit board
22
. Two conductive paths connect substrate
14
to capacitor
16
, and two other conductive paths connect substrate
14
to capacitor
24
.
In an integrated circuit, there are typically two types of connections made to a substrate. First, there are input/output (I/O) connections which typically connect the substrate to external environment signal sources and signal destinations. Second, there are core connections which provide connections between internal substrate circuits and components such as capacitors and resistors. Core connections have no external signal sources or signal destinations associated with them, and are typically centered on the substrate, completely surrounded by I/O connections.
Capacitors
16
and
24
are provided as examples of components designed into a system for the purpose of filtering signal frequencies from a conductive path. Although these capacitors function properly for their intended purpose, the conductive paths between the substrate and each of capacitors
16
and
24
have a characteristic high inductance which inhibits the use of high signal frequencies.
It is well known in the art that inductances impede the passage of signals at higher frequencies, and capacitances impede the passage of signals at lower frequencies. Two possibilities exist for reducing impedances.
First, the impedance of the signal path may be reduced as disclosed in U.S. patent application Ser. No. 09/320,240, entitled “Peripheral Core Bumps for low inductance paths for Chip Capacitors” naming Bidyut Sen as inventor, filed May 26, 1999, and assigned to Sun Microsystems, Inc., the application being incorporated herein by reference in its entirety.
Second, the inductances associated with the capacitors themselves may be reduced. Prior art capacitors have undesirably high impedances associated with them which, if eliminated or reduced, would allow higher signal frequencies to pass at desirable signal levels.
It would therefore be beneficial to provide a capacitor which reduces the inherent inductance while maintaining or increasing the capacitance.
SUMMARY OF THE INVENTION
A capacitor is disclosed herein, including a substrate, a first interconnect layer disposed upon the substrate and a first insulating layer disposed on the first interconnect layer. A first metal layer is disposed on the first insulating layer and formed as at least two regions, the at least two regions of the first metal layer connected to the first interconnect layer through vias. A second insulating layer is disposed on the first metal layer. A second metal layer is disposed on the second insulating layer and is formed as at least two regions. The capacitor further includes a third insulating layer disposed on the second metal layer, a second interconnect layer disposed on the third insulating layer and connecting to the at least two regions of the second metal layer through vias. Finally, a first terminal is connected to the first interconnect layer and a second terminal is connected to the second interconnect layer.


REFERENCES:
patent: 5774326 (1998-06-01), McConnelee
patent: 5874770 (1999-02-01), Saia et al.
patent: 6025226 (2000-02-01), Gambino et al.

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