Semiconductor device manufacturing: process – Forming bipolar transistor by formation or alteration of... – Including diode
Reexamination Certificate
2001-12-07
2003-06-17
Ho, Hoai (Department: 2818)
Semiconductor device manufacturing: process
Forming bipolar transistor by formation or alteration of...
Including diode
C257S551000
Reexamination Certificate
active
06579772
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, which may be used as, for example, a semiconductor rectifying element having low reverse breakdown voltage such as a voltage regulator diode (Zener diode), and a manufacturing method thereof.
2. Description of the Related Art
A semiconductor diode
1
such as the voltage regulator diode shown in
FIG. 1
is known. This semiconductor diode
1
may have, for example, a simple three-layer structure embracing an n-type semiconductor region
2
having a high impurity concentration, an n-type semiconductor region
3
having predetermined specific impurity concentration, and a p-type semiconductor region
4
having a high impurity concentration. In addition, on the top surface of n-type semiconductor region
2
and the bottom surface of p-type semiconductor region
4
, there may be formed metal films
5
,
6
, which serve as the respective electrodes thereof.
Typically, with a semiconductor diode having such a stacked structure, there exists a strong electric field in the depletion layer of a p-n junction to which a reverse bias voltage is applied; however, at the chip sidewall, whereat the terminal portion of the p-n junction is exposed, it may be influenced by the impurities, ions, or the like adhered to the surface, and the electric field may become even stronger in places making it easier for breakdowns to occur. As a result, with the semiconductor diode, it becomes difficult to obtain a reverse breakdown voltage that is theoretically expected. Therefore, in order to reduce the electric field at the chip sidewall
7
of the semiconductor diode
1
as shown in
FIG. 1
, the chip sidewall
7
exposing the terminal portions of the p-n junction is cut so as to form the necessary angle with the p-n junction interface
9
employing a beveled structure, which is made to reduce the electric field. By employing such beveled structure, the electric field at the chip sidewall
7
may be decreased and breakdowns made to occur throughout the entirety of the junction interface, resulting in stabilization of the device performance, achieving the constant breakdown voltage. It may be noted that, as is well known, by employing a beveled structure in a power semiconductor device having higher breakdown voltage than the voltage regulator diode, the breakdown voltage can be improved.
Nevertheless, as described in the following, there are problems with the semiconductor diode
1
shown in FIG.
1
.
(1) With the semiconductor diode
1
shown in
FIG. 1
, during the assembling process, after the chip sidewall
7
is subjected to a wet cleansing process using an acidic or alkaline chemical to protect them from the external environment, the chip sidewall
7
is covered with an insulating layer
8
. However, product evaluation testing results for the semiconductor diode
1
manufactured in this manner indicated points where the performances and quality of the product were not stabilized. The changes in the surface state and surface damage to the chip sidewall
7
imparted by the wet cleansing and the covering thereof by the insulating layer
8
were given as the reasons for the poor performances, and so on, not being stabilized. Since the surface state of an actual semiconductor chip is extremely active, it is extremely difficult to control the precision and reproducibility of such surface state.
(2) In the semiconductor diode
1
shown in
FIG. 1
, the breakdown voltage is determined by the impurity concentration in the n-type semiconductor region
3
at the p-n junction between the n-type semiconductor region
3
and the p-type semiconductor region
4
. However, in order to determine this breakdown voltage, the resistivity &rgr; of the semiconductor wafer (silicon wafer) used in manufacturing process needs to be controlled with great precision. As a result, it becomes necessary to specially order a custom-made semiconductor wafer having a strictly defined resistivity &rgr; from a semiconductor wafer manufacturer, and carefully test it after delivery as well. Therefore, a problem lies in the semiconductor wafer being costly. As an example, silicon wafers having a resistivity within the narrow range of 0.01 to 0.03 &OHgr;·cm—which corresponds to the impurity concentration range of approximately 5×10
18
/cm
3
to 7×10
17
/cm
3
with the n-type silicon—have been conventionally custom-ordered.
(3) When manufacturing the semiconductor diode
1
shown in
FIG. 1
, in order to have a beveled structure by forming the chip sidewall
7
at a slant angle relative to the p-n junction plane, a problem lies in the manufacturing processes increasing in number due to the addition of various processes such as sandblasting, grinding, polishing or etching.
(4) In the assembling process of the semiconductor diode
1
shown in
FIG. 1
, chips cut from a semiconductor wafer are scheduled to be packaged. However, since the chip sidewalls of the respective chips are at the slant angle relative to the top/bottom surfaces of the chips, it requires much effort to load the respective chips onto jigs, such as the collets.
The present invention has come about in order to solve the above problems. Therefore, an object of the present invention is to provide a semiconductor device preventing the development of localized breakdown at the chip sidewall exposing a p-n junction, obtaining a stabilized, desired breakdown voltage.
Another object of the present invention, is to provide a semiconductor device and manufacturing method thereof, which allows for a reduction in cost of the semiconductor wafer and allows for the range of allowable resistivity &rgr; of the semiconductor wafer used to be widened.
Still another object of the present invention is to provide a semiconductor device manufacturing method, which allows chip surface passivation processing to be simplified or to be abbreviated.
Still another object of the present invention is to provide a semiconductor device and a manufacturing method thereof, which allows the manufacturing process to be simplified.
Yet still another object of the present invention is to provide a semiconductor device allowing for favorable handling and favorable loading of the chip into a jig, such as the collet, during the product assembly process.
SUMMARY OF THE INVENTION
In order to solve the aforementioned problems, a first aspect of the present invention inheres in a semiconductor device encompassing (a) a first semiconductor region of a first conductivity-type including a first end surface, a second end surface opposite the first end surface and a first outer surface connecting the first and second end surfaces; (b) a second semiconductor region of the first conductivity-type having a third end surface, a fourth end surface opposite the third end surface and a second outer surface connecting the third and fourth end surfaces, wherein the fourth end surface is in contact with the first end surface; (c) a third semiconductor region of a second conductivity-type, which is in contact with the first semiconductor region at the second end surface; and (d) fourth semiconductor region having an inner surface in contact with the first and second outer surfaces and an impurity concentration lower than the first semiconductor region, which is in contact with the third semiconductor region. Here the second conductivity type is the opposite conductivity type as the first conductivity type. More specifically, if the first conductivity type is assigned to be n-type, then the second conductivity type is p-type; and if the first conductivity type is assigned to be p-type, then the second conductivity type is n-type. The first conductivity type or the second conductivity type may further be an intrinsic semiconductor. For example, two p-n junction interfaces may be implemented by bringing both a high impurity concentration n-type first semiconductor region and relatively low impurity concentration n-type fourth semiconductor region into contact with a p-type third semiconductor region. Alternativel
Ho Hoai
Hoang Quoc
Kilpatrick & Stockton LLP
Sanken Electric Co. Ltd.
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