Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
1998-03-10
2001-02-06
Ngo, Ohuong Dinh (Department: 2787)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
Reexamination Certificate
active
06185595
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a technique for processing image data and a technique for decompressing the compressed image data and, more particularly, to a technique which is useful when applied to a discrete cosine transformation operation circuit in the JPEG (Joint Photographic Experts Group) system or the MPEG (Motion Picture Experts Group) system.
BACKGROUND ART
In the prior art, the discrete cosine transformation (DCT) operation circuit is equipped with a plurality of multipliers for multiplying input data and DCT transformation coefficients.
In the case of a DCT matrix operation composed of 8 rows and 8 columns (8×8), as generally used in the JPEG system or the MPEG system, for example, there are provided eight multipliers.
However, the multiplier is equipped with a number of gates to raise a drawback that the gate scale of the entire operation circuit is enlarged. In addition, the operating frequency of the multipliers is equal to the frequency (which is equal to the frequency of the inputting timing of the input data) of the outputting timing of the DCT operation result, and the product of their ratio (i.e., “1”) and the number of multipliers is as large as “8” to raise another drawback that the power consumption is increased. Specifically, the multipliers are driven with a high operating frequency, so that they consume a high power when driven. The number of the multipliers is as large as eight in the prior art so that the power consumption is further increased.
As a measure for improvement, there is disclosed in Japanese Patent Laid-Open No. 4-280368, a DCT operation circuit which is constructed by using two multipliers operated with a frequency four times as high as that of the inputting timing of the data inputted to the DCT operation circuit. In this DCT operation circuit, for example, an input data x
11
is multiplied by DCT transformation coefficients d
11
, d
21
, d
31
and d
41
by one multiplier, and by DCT transformation coefficients d
51
, d
61
, d
71
and d
81
by the other multiplier, thereby obtaining four multiplication results x
11
d
11
, x
11
d
21
, x
11
d
31
and x
11
d
41
, and four multiplication results x
11
d
51
, x
11
d
61
, x
11
d
71
and x
11
d
81
. The eight multiplication results thus obtained are stored in eight registers.
Another input data x
21
is also multiplied by DCT transformation coefficients d
12
, d
22
, d
32
and d
42
by one multiplier and by DCT transformation coefficients d
52
, d
62
, d
72
and d
82
by the other multiplier, thereby obtaining four multiplication results x
21
d
22
, x
21
d
22
, x
21
d
32
and x
21
d
42
, and four multiplication results x
21
d
52
, x
21
d
62
, x
21
d
72
and x
21
d
82
. The eight multiplication results thus obtained are stored in eight registers. Moreover, the eight multiplication results x
21
d
12
, x
21
d
22
, x
21
d
32
, x
21
d
42
, x
21
d
52
, x
21
d
62
, x
21
d
72
and x
21
d
82
and the preceding eight multiplication results x
11
d
11
, x
11
d
21
, x
11
d
31
, x
11
d
41
, x
11
d
51
, x
11
d
61
, x
11
d
71
and x
11
d
81
read out from the foregoing eight registers are added by adders, and the addition results are stored again in the aforementioned eight registers.
By repeating the operation composed of such multiplication and cumulative addition eight times, the elements y
11
to y
81
of the matrix are determined. By repeating the operation eight times, moreover, all the elements of the matrix are determined. Thus, the one-dimensional 8×8 DCT matrix operation is ended.
In the DCT operation circuit disclosed in Japanese Patent Laid-Open No. 4-280368, however, two multipliers are used and therefor improvement in the circuit scale is still needed. In other words, the number of multipliers is desirably reduced to one so that the circuit scale may be minimized.
In the DCT operation circuit of the aforementioned Laid-Open, moreover, the multipliers are operated with a frequency four times as high as that of the inputting timing of the data inputted to the DCT operation circuit. As a result, the product of the ratio (hereinafter referred to as the “normalized frequency”) of the operating frequency of the multipliers to the frequency of the inputting timing of the data and the number of multipliers is “8”, and no improvement has been made in the power consumption. In order to reduce the power consumption, the product of the normalized frequency and the number of multipliers is desired to be minimized as much as possible.
The invention has been made in view of the circumstances and has a main object to provide a discrete cosine transformation operation circuit whose power consumption is reduced by setting the product of the number of multipliers of a one-dimensional discrete cosine transformation operation circuit and the normalized frequency at
4
and to reduce the circuit scale by setting the number of multiplier at
1
.
The foregoing and other objects and novel features of the invention will become apparent from the following description to be made with reference to the accompanying drawings.
DISCLOSURE OF INVENTION
The summary of representatives of the aspects of the invention to be disclosed herein will be described in the following.
In the discrete cosine transformation operation circuit of the invention, more specifically, there is provided one multiplier which is operated with a frequency four times as high as that of the inputting timing of the data to be inputted to the discrete cosine transformation operation circuit to sequentially multiply the elements of the DCT transformation coefficients and the elements of the input data respectively. The multiplication results are added by the cumulative adder to determine a pair of cumulative addition results which correspond to the sums and differences of the paired elements of the data to be outputted from the discrete transformation operation circuit. The operations for determining the paired elements of the output data by adding and subtracting the cumulative addition results by the adder and the subtracter specific times the number of which is one-half of the number of elements of the column of the matrix of the input data. All the elements of the matrix of the output data are determined by performing those operations specific times the number of which is equal to the number of elements of the row of the matrix of the input data.
In the discrete cosine transformation operation circuit of the invention, more specifically, there is provided one multiplier which is operated with a frequency four times as high as that of the inputting timing of the data to be inputted to the discrete cosine transformation operation circuit to sequentially multiply the elements of the DCT transformation coefficients by the elements of the input data respectively. The multiplication results are added as they are by the first cumulative adder, and the signs are alternately inverted to perform addition by the second cumulative adder specific times the number of which is one-half of the number of elements of the row of the matrix of the input data, and thereby to determine the elements of the column of the matrix of the output data. These operations are performed specific times the number of which is equal to the number of elements of the column of the matrix of the input data to determine all the elements of the matrix of the output data.
Moreover, there are provided two multipliers to be operated with a frequency two times as high as that of the inputting timing of the data to be inputted to the discrete cosine transformation operation circuit, the DCT transformation coefficients are divided into two sets and stored in a ROM so that the respective multiplications of the elements of the sets of the DCT transformation coefficients and the elements of the input data may be simultaneously performed by the two multipliers.
One or both of the discrete cosine transformation operation circuits are used to construct a two-dimensional discrete cosine transformation operation circuit comprising: a pair of one-dimensional discrete cosine tra
Hase Masaru
Hori Toyokazu
Sumi Nario
Hitachi , Ltd.
Mattingly Stanger & Malur, P.C.
Ngo Ohuong Dinh
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