Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
2000-09-18
2004-05-04
Ngo, Chuong Dinh (Department: 2124)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
C708S400000
Reexamination Certificate
active
06732131
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 11-280673, filed on Sep. 30, 1999, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention relates to a discrete cosine transformation (DCT) apparatus and an inverse discrete cosine transformation (IDCT) apparatus which are often employed for compression and decompression of picture data and particularly to a discrete cosine transformation apparatus and an inverse discrete cosine transformation apparatus for allowing a two-dimensional transformation to be carried out in a one-dimensional transformation circuit.
The discrete cosine transformation is generally used for video compression such as in a digital television broadcast system. Conventionally, the application of higher operating clock frequencies was not easy. As the operating clock in LSIs has successfully been shifted to higher frequencies, two-dimensional transformation is now feasible with the use of a single one-dimensional DCT or IDCT circuit operated two times for video compression/decompression of e.g. a high-definition TV system. Such a scheme of the circuit arrangement contributes to the scale down of the entire circuit size of an LSI, hence permitting the price to be reduced.
However, when one-dimensional processing is shifted to two-dimensional processing over every input of less than eight-point data, such as one-point (one pixel or one coefficient) unit or a two-point unit, it is necessary to provide in the one-dimensional transformation circuit a register for saving the results of intermediate operation between the one-dimensional processing and the two-dimensional processing. The register has a significant size substantially equal to the scale of a two-dimensional transformation circuit, hence failing to minimize the overall circuit size.
FIG. 18
illustrates a related technique of switching each block of data between the one-dimensional processing and the two-dimensional processing with the use of an eight-point transformation processor which receives the data at a rate of two units of data per clock period and outputs two eight-point transformed data for every one clock period. As the delay of output due to the arithmetic operation extends throughout substantially seven clock periods, the transposed output is enabled only after the four clock periods from the completion of input of one-dimensional transformed data. More specifically, the transformation of one block yields an invalid operation of four clock periods. Also, as the write (output of one-dimensional transformed data) and the read (input of one-dimensional transformed data for two-dimensional transformation) are executed simultaneously in substantially four clock periods for every 68 clocks, the transposition memory has to be implemented by two-port RAM (random access memory) and its area size will hardly be reduced. Furthermore, the input and output are discontinuous from one block to another. For smoothing the operation at one data per clock period, the input and the output of the data require a memory size of 32 coefficients, respectively.
FIG. 19
illustrates another related technique of switching each block between the one-dimensional processing and the two-dimensional processing with the use of a one-port RAM as the transposition memory, hence reducing the RAM area to a half. For preventing the read and the write from occurring on the transposition memory, the start of the read is further delayed by four clock periods from that shown in FIG.
18
. This will extend the invalid operation per block to eight clock periods, thus declining the operational efficiency. Similar to the operation shown in
FIG. 18
, the input and the output are discontinuous from one block to another. For smoothing the input and output data to one data per clock period, the memory size of 32 coefficients may be required for the input and output operation, respectively.
FIG. 20
illustrates a further another related technique of switching in every two blocks between the one-dimensional processing and the two-dimensional processing in order to eliminate the invalid operation period generated in processing every block. However, the transposition memory requires a memory capacity of two blocks since the one-dimensional processing and the two-dimensional processing are switched in every two blocks. Also, as the read and the write are executed once, like the related technique shown in
FIG. 18
, the transposition memory may be implemented by a two-port type RAM hence increasing the memory area size to four times greater than that shown in FIG.
19
.
In that case, the input and output of data are discontinuous on the basis of two blocks. For smoothing the input and output data to one data per clock period, the memory size of 64 coefficients may be needed for the input and output, respectively.
While switching between the one-dimensional processing and the two-dimensional processing is conducted in every one block or every two blocks, the read and the write are executed at one time. As a result, the transposition RAM area will hardly be decreased or the operational efficiency will be declined. Also, for preventing the input and output of data from being discontinuous constantly, a significant size of the data memory is required. More specifically, while the one-dimensional transformation circuit remains not increased in the size, the transposition memory may increase in the size or its operational efficiency may be declined.
BRIEF SUMMARY OF THE INVENTION
It is an object of the present invention to provide a orthogonal transformation apparatus, such as a discrete cosine transformation apparatus or an inverse discrete cosine transformation apparatus, in which declination of the operational efficiency can be minimized even when data blocks cannot be input at predetermined intervals and two-dimensional orthogonal transformation can be performed with the use of a small circuit arrangement.
According to the present invention, there is provided a discrete cosine transformation apparatus comprising a transposition section which transposes input picture signal of N×N pixels between one-dimensional processing and two-dimensional processing, and a transformation section which subjects an output of the transposition section to a discrete cosine transformation.
According to the present invention, there is provided an inverse discrete cosine transformation apparatus comprising a transposition section which transposes input DCT coefficients of N×N in every N coefficients between one-dimensional processing and two-dimensional processing, and a transformation section which subjects an output of the transposition section to an inverse discrete cosine transformation.
According to the present invention, there is provided a discrete cosine transformation/inverse discrete cosine transformation apparatus comprising a single N-point transformation processor which switches in every N points between the one-dimensional processing and the two-dimensional processing to perform orthogonal transformation of N×N points.
According to the present invention, there is provided a discrete cosine transformation apparatus comprising an input processor which outputs data input one by one, at a rate of 2M data per clock period for M clock periods, an N-point transformation section which N-point transforms data input at the rate of 2M data per clock period from the input processor and outputs the transformed data at the rate of 2M data per clock period, an output processor which continuously outputs the one-dimensionally transformed data input at the rate of 2M data per clock period from the N-point transformation processor at the rate of 2M data per clock period for every N/2M clock periods while rounding N two-dimensionally transformed data input at the rate of 2M data per clock period in the succeeding N/2M clock periods, and a transposition processor which transposes N×N da
Do Chat C
Kabushikikaisha Toshiba
Ngo Chuong Dinh
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